2.1.

System Configuration

The whole system embodies an array of microcolumns, each having an nc-Si electron emitter array in combination with microminiaturized electron optical elements for projecting a reduced image ($1/100$) of focused e-beams. The microcolumns have very small physical dimensions, and they are made by utilizing MEMS fabrication technology. The result is a compact overall mechanical system with substantial cost benefits. Figure 1 shows the configuration of the miniaturized column consisting of the active matrix nc-Si electron emitter array, an array of condenser lenses, anode plates, a rotation coil, telecentric reduction lenses, deflectors, and collection optics providing functions of dynamic focusing, alignment collection, and deceleration. Also embedded are metrology systems, i.e., a stigmator for astigmatism correction and a Faraday cup for real-time monitoring of the projected pixel images.

Fig. 1

Configuration of the miniaturized column having an active-matrix nc-Si electron emitter array in combination with microminiaturized electron optical elements.

The nc-Si emitters are arranged in a $1,000\times 1,000$ pixels array with a pitch size of 10 μm. The array covers an area of $10\times 10{\mathrm{mm}}^2$ and is integrated with the active-matrix driving LSI. The one million beamlets projecting pixels simultaneously are switched on and off by changing the CMOS-compatible voltage. The constitutive array of condenser lenses consists of a grid of electrostatic Einzel-type lenslets, which collimate the emitted electron beams from the emitter. The array of lenslets is separately fabricated and mechanically bonded onto the array of nc-Si emitters (see Fig. 1). The bonding process is currently under development in which each is aligned in a one-to-one manner with the required accuracy of a submicrometer by using a piezo-actuated manipulator under in-situ scanning electron microscope (SEM) observation of the fabricated alignment marks. Fabrication of monolithically integrated lenslets with the array of nc-Si emitters are also being studied in parallel. The nc-Si emitter exhibits favorable emission properties in terms of its perpendicularity (i.e., lower emission angle) and uniformity over the whole surface,¹² originating from the ballistic transfer of electrons passing through the nanosilicon-wired-array structures. This feature allows the condenser lenses to be easily designed so as to collimate and focus the emitted electrons, leading to reduced beam size ($1/10$) and increased current density ($\times 100$) for each electron beam without any change in pitch size (10 μm). Each of the electron beamlets passing through the array of condenser lenses is accelerated at the anode plate through apertures with an acceleration voltage of $\sim 20\mathrm{keV}$. The beamlets then enter a telecentric reduction lenses consisting of two electromagnetic lenses. Here, they are focused to project a reduced image onto the wafer. The two embedded deflectors scan the focused beamlets to perform the direct-write operation in synchronization with the controlled motion of the stage.

2.2.

Compensation of Chromatic and Spherical Aberrations

Since a general rotationally symmetric lens system cannot make a concave lens creating a negative aberration, neither chromatic nor spherical aberration can be compensated by optimizing the configuration of the electric and magnetic fields in the electron optics presented in Fig. 1. Chromatic aberration is inherently generated by the energy dispersion of the emitted electrons, and this restricts the practical resolution of the system. Our previous study demonstrates that the initial energy dispersion of emitted electrons from an nc-Si ballistic emitter is innately small (approximately 2 eV at RT and 500 meV at 100 K),^11,13,14 and thus, the chromatic aberration can be sufficiently optimized by making the energy distribution as close to monochromatic as possible. In this regard, we are improving the physical properties of nc-Si itself, as well as exploring other potential schemes such as operating the emitter at a lower temperature, which has been demonstrated to significantly reduce energy spread of the emitted electrons.^11,13,14 On the other hand, spherical aberration should be compensated on a reduced image projected by the telecentric reduction lens system in order to improve the practical resolution. It can be corrected by controlling each of the driving voltages in the picture cells of the integrated LSI, so that the spatial distribution of the emitted beamlets’ energy can be adjusted to compensate for the spherical aberration and be balanced on the projected image. At present, we are studying how to incorporate such a function into the next design of the LSI.

3.1.

Evaluation of Emission Characteristics from Prototype Dot Pattern Array of nc-Si Emitters

The active-matrix electron emitter includes an array of nc-Si dot patterns, each connected electrically to through silicon via (TSV) plugs from the back side of the supportive substrate. The device consists of an aligned joint of the TSV plugs with driving pads on the active-matrix LSI. In prototyping this device, a test structure was preliminary fabricated to ascertain if the electron emissions from the array would work in practice; a 2-μm-thick nondoped columnar polycrystalline silicon (poly-Si) film was deposited on a 4-inch $n^{+}$-type Si substrate, and the poly-Si was dry-etched with a photoresist mask to form an array of $100\times 100$ dots with a pitch of 50 μm, each dot having an area of $20\times 20$ μm². After that, a 0.15-μm-thick ${\mathrm{Si}}_3{\mathrm{N}}_4$ film was deposited over the whole wafer surface by low-pressure chemical vapor deposition (LPCVD). Then, apertures were opened on the ${\mathrm{Si}}_3{\mathrm{N}}_4$ film with a photoresist mask at the top surfaces of the dots by highly selective reactive-ion-etching (RIE) of the ${\mathrm{Si}}_3{\mathrm{N}}_4$ film over the underlying poly-Si layer in a mixture of ${\mathrm{CHF}}_3/{\mathrm{CF}}_4$ gas. After the individual poly-Si top surfaces were exposed, each was selectively anodized in a HF solution, which promoted preferential local dissolution at the poly-Si grain boundaries and resulted in structured porous silicon. Because of the columnar geometry of the poly-Si grains, the fabricated porous silicon includes nanodots with columnar/vertically arranged interconnections similar to nanometric wires (“nanowires”).

The anodization was conducted as follows: The processed 4-inch wafer was diced into 12 pieces; each specimen measured $20\times 20{\mathrm{mm}}^2$ and was grooved into a working electrode of a Teflon sample holder in contact with the backside surface. This was followed by mechanical screw-clamping of the top surface to seal the back surface from the solution (see Fig. 2). An anodic current was galvanostatically applied for 6 s to the working electrode in a solution of HF (55%): ${\mathrm{C}}_2{\mathrm{H}}_5\mathrm{OH}=1:1$ at a current density of $25\mathrm{mA}/{\mathrm{cm}}^2$ under the irradiation of a tungsten lamp.

Fig. 2

Electrochemical etching of patterned poly-Si for structuring a Si nanowire array.

After that, the sample was treated with rapid-thermal-oxidation (RTO) at 900°C in a dry ${\mathrm{O}}_2$ ambient for 25 min to form a thin oxide layer surrounding each Si nanodot in the nanowire array. The surface was then treated with high pressure water vapor annealing (HWA) at 1.3 MPa and 260°C for 3 h and subsequent super critical rinse and dry (SCRD) in order to obtain sufficiently passivated nc-$\mathrm{Si}/{\mathrm{SiO}}_2$ interfaces. The interfaces had an extremely low defect density, because of the minimized mechanical stress of the surrounding ${\mathrm{SiO}}_2$.¹⁵ Then, a $\mathrm{Cr}/\mathrm{Au}$ ($=300\mathrm{nm}$) common electrode was selectively RF-sputtered by using a liftoff process with resist mask onto an area excluding the top surfaces of the dots. This was followed by depositing a $\mathrm{Ti}/\mathrm{Au}$ ($=1\mathrm{nm}/9\mathrm{nm}$) surface electrode over the whole surface. This two-step deposition process improves step coverage for each dot pattern, even for extremely thin surface electrodes. Figure 3(a) shows an SEM image of the fabricated test structure array consisting of a $100\times 100$ dots pattern of nc-Si emitters. The corresponding structure is schematically illustrated in Fig. 3(b).

Fig. 3

(a) SEM image of the fabricated test structure of a $100\times 100$ array of nc-Si emitters with a pitch of 50 μm, with each emitter having an area of $20\times 20$ μm²; (b) schematic illustration of the corresponding structure.

Figure 4(a) shows the characteristics of the diode current density $J_{\mathrm{ps}}$ and corresponding emission current density $J_e$ as a function of applied voltage ${\mathrm{V}}_{\mathrm{ps}}$ obtained from the sample shown in Fig. 3. The measurement circuit is displayed in the upper part of the figure. The $J_e$ plot shows electron emissions from the emitter array at $>4.5\mathrm{V}$ exceeding the work function of the Au electrode. The current density reached 10 μA/cm² at 15 V, which corresponds to an amplified electron current density of $1\mathrm{mA}/{\mathrm{cm}}^2$ passing through the integrated condenser lenslets ($\times 100$) (see Fig. 1). Figure 4(b) is a Fowler-Nordheim (FN) plot obtained from the emission curve in Fig. 4(a). It should be noted that the linear behavior covered the whole range of applied voltage, although the emission exhibited variability in the low voltage region ($<10\mathrm{V}$), presumably due to a space charge effect of the emitted electrons with relatively low kinetic energy. The linearity of the FN plot suggests that electrons were ballistically transported via cascade tunneling through interconnected nanodots in the silicon nanowires.

Fig. 4

(a) Characteristics of diode current density $J_{\mathrm{ps}}$ and corresponding emission current density $J_e$ vs. applied voltage ${\mathrm{V}}_{\mathrm{ps}}$; (b) Fowler-Nordheim plot obtained from Fig. 4(a).

3.2.

Fabrication of nc-Si Emitter Array on SOI Substrate for Integration with the Active-Matrix Driving LSI

nc-Si emitters were fabricated on SOI substrate with via-last processed TSV plugs connected to the array from the back side, with each plug and emitter forming an aligned joint with driving pads on the active-matrix LSI.

The essential features of the fabrication process are illustrated in Fig. 5. As shown in this figure, a 2-μm-thick nondoped columnar poly-Si film is deposited on a 4-inch SOI wafer having an $n^{++}$-type active layer (0.005 Ωcm). The active layer/poly-Si stacking structure with a photoresist mask is dry etched, until the underlying active layer on the BOX is 50 nm thick. The resulting array of $100\times 100$ dots covers an area of $20\times 20$ μm² (steps 1-2). Next, ${\mathrm{CF}}_4/{\mathrm{CHF}}_3$ RIE is used to conduct a highly selective sidewall-spacer etching of 0.15-μm-thick LP-CVD ${\mathrm{Si}}_3{\mathrm{N}}_4$ over the underlying active layer (step 3). After the wafer is diced into smaller specimens, these smaller specimens are anodized in a HF solution with the electrochemical cell shown in Fig. 2. Immediately after that, they are treated with $\mathrm{RTO}+\mathrm{HWA}+\mathrm{SCRD}$ under the same conditions described in Sec. 3.1 (step 4). Then, $\mathrm{Ti}/\mathrm{Cu}$ via-filled TSV plugs (steps 5 to 6), solder bonds with the active-matrix LSI through the Au–Sn bump structures (step 7), and electrodes (step 8) are formed.

Fig. 5

Schematic illustration of the fabrication process flow of an nc-Si emitter array integrated with active-matrix driving LSI. The nc-Si emitter array was fabricated on SOI substrate with via-last processed TSV plugs.

Galvanostatically anodizing the structure fabricated on an SOI substrate (step 4) leads to an extremely high potential due to the difficulty of injecting carriers through the BOX layer if the working electrode is connected only to the back of the sample. In fact, the potential reached several tens of volts when an anodic current was applied under the galvanostatic condition of $25\mathrm{mA}/{\mathrm{cm}}^2$; such a situation is probably accompanied by an undesirable BOX breakdown process. Thus, during the anodization process in step 4, the working electrode was connected directly to the top surface, bypassing the remaining $n^{++}$ active layer in the upper part of the surrounding sidewall of the grooved substrate. The remaining $n^{++}$ active layer among the dots was dissolved and became porous and easily oxidized to form an insulating layer in the subsequent RTO treatment. This layer formed a self-aligned electrical separation among the dots, resulting in complete separation of the pixels.

Nanostructures constituting the nc-Si cause the band gap to widen due to the quantum confinement effect.¹⁶ Experimentally exposing a YAG Laser (266 nm) on an anodized poly-Si surface on SOI substrate with subsequent $\mathrm{RTO}+\mathrm{HWA}$ treatments under the same conditions as described in step 4 led to red band photoluminescence (PL) with a peak intensity at a wavelength of $\sim 700\mathrm{nm}$ (1.8 eV) (see Fig. 6). This indicates that Si nanowire array structures with a derived size of $\sim 3\mathrm{nm}$ were formed.¹⁶ Electron emissions were also observed from this sample through a subsequently deposited $\mathrm{Ti}/\mathrm{Au}$ ($=1\mathrm{nm}/9\mathrm{nm}$) electrode on the top surface in association with applied voltage, demonstrating that the anodizing process is workable on an SOI substrate, as well as on Si.

Fig. 6

Photoluminescence (PL) spectra obtained from anodized nondoped ply-Si surfaces on SOI substrate with subsequent treatments of RTO and $\mathrm{RTO}+\mathrm{HWA}$.

Figure 7(a) shows an SEM image of the structure just after step 4 in Fig. 5. The corresponding structure is schematically illustrated in Fig. 7(b). The anodizing process in step 4 could be conducted at a lower applied anodic-voltage ($\sim 3\mathrm{V}$) for galvanizing the $25\mathrm{mA}/{\mathrm{cm}}^2$. As shown in Fig. 7(a), a $100\times 100$ array of nc-Si emitters with a pitch of 50 μm, each having an area of $20\times 20$ μm², was successfully formed on the SOI substrate. Cross-sectional SEM observation showed that the layer remaining among the dot patterns was sufficiently oxidized as an insulating layer, and the thickness was approximately 50 nm over the whole surface.

Fig. 7

(a) SEM image of a $100\times 100$ array of nc-Si emitters fabricated on SOI substrate with a pitch of 50 μm, with each emitter having an area of $20\times 20$ μm²; (b) schematic illustration of the corresponding structure.

3.3.

Advanced Fabrication Process for nc-Si Emitter Array

The results described in Secs 3.1 and 3.2 demonstrated that the array of $100\times 100$ microminiaturized nc-Si emitters worked in practice by emitting ballistic electrons and was manufacturable on an SOI substrate, thereby enabling us to integrate it with an active-matrix driving LSI. However, the fabrication process shown in Fig. 5 remains a challenge for processing larger wafers for mass production in terms of SOI usage related to cost benefit, as well as the manufacturability of the anodization process. Figure 8 shows an advanced structure and corresponding fabrication process flow to address these issues. Here, the nc-Si emitter array is fabricated on a Si substrate with via-first processed TSV plugs filled with an $n^{++}$-type LP-CVD poly-Si film. All of the processes are done on 4-inch Si wafer, and they can be extended to larger wafer processes. Since most of the processes shown in Fig. 8 include many of the processes described in the previous section, only the essential features will be described here.

Fig. 8

Schematic illustration of the advanced process flow for fabricating an nc-Si emitter array integrated with active-matrix driving LSI. The nc-Si emitter is fabricated on Si substrate with via-first processed TSV plugs.

A 200-μm-thick 4-inch Si wafer (p-type, 5k Ωcm) is deep-reactive-ion-etched (Deep-RIE) with a photoresist mask to open through-silicon-vias (15 μm in diameter) with a pitch of 50 μm, and a thermally grown ${\mathrm{SiO}}_2$ layer is formed over the whole surface (steps 1-2). Next, an $n^{++}$-type LP-CVD poly-Si film is deposited over the whole surface to completely fill the vias, and both surfaces are chemical-mechanical polished (CMP) until the remaining $n^{++}$-poly-Si thickness on one surface is thinner ($\sim 2$ μm) than the thickness on the other surface (step 3). After that, a 2-μm-thick nondoped columnar poly-Si film is deposited on the thinner side, and a $200\times 200$ array of dots with a pitch of 50 μm (each dot having an area of $20\times 20$ μm²) is formed on the $n^{++}$-poly-Si/nondoped poly-Si stack structure (step 4). Next, thermally grown ${\mathrm{SiO}}_2$ film and LP-CVD ${\mathrm{Si}}_3{\mathrm{N}}_4$ film are deposited and patterned on the top surfaces of the dots (step 5). Subsequently, each exposed poly-Si surface is anodized by galvanostatically applying an anodic current from the back of the $n^{++}$-poly-Si film (step 6). After $\mathrm{RTO}+\mathrm{HWA}+\mathrm{SCRD}$ treatment, the back side $n^{++}$-poly-Si is patterned as an electrode, and an aligned joint with driving pads is formed on the active-matrix LSI through Au-Si eutectic bonding (step 7). Finally, a $\mathrm{Ti}/\mathrm{Au}$ surface electrode is formed, and half-cut dicing is done to expose the bonding pads of the LSI (step 8).

This advanced process yields not only cost benefits by using Si substrate instead of SOI, but also increased manufacturability for mass production in the anodization process by applying a uniform galvanostatic current to each dot from the back of the wafer through each filled via.