31 July 2018 Self-aligned blocking integration demonstration for critical sub-30-nm pitch Mx level patterning with EUV self-aligned double patterning
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Abstract
We report a sub-30-nm pitch self-aligned double patterning (SADP) integration scheme with EUV lithography coupled with self-aligned block technology targeting the back end of line metal line patterning applications for logic nodes beyond 5 nm. The integration demonstration is a validation of the scalability of a previously reported flow, which used 193-nm immersion SADP targeting a 40-nm pitch with the same material sets (Si3N4 mandrel, SiO2 spacer, spin on carbon, spin on glass). The multicolor integration approach is successfully demonstrated and provides a valuable method to address overlay concerns and, more generally, edge placement error as a whole for advanced process nodes. Unbiased line edge roughness (LER)/line width roughness (LWR) analysis comparison between EUV SADP and 193-nm immersion SADP shows that both integrations follow the same trend throughout the process steps. While EUV SADP shows increased LER after mandrel pull, metal hardmask open, and dielectric etch compared to 193-nm immersion SADP, the final process performance is matched in terms of LWR (1.08-nm 3 sigma unbiased) and is 6% higher than 193-nm immersion SADP for average unbiased LER. Using EUV, SADP enables almost doubling the line density while keeping most of the remaining processes and films unchanged and provides a compelling alternative to other multipatterning integrations, which present their own sets of challenges.
© 2018 Society of Photo-Optical Instrumentation Engineers (SPIE) 1932-5150/2018/$25.00 © 2018 SPIE
Angélique Raley, Joe Lee, Jeffrey T. Smith, Xinghua Sun, Richard A. Farrell, Jeffrey Shearer, Yongan Xu, Akiteru Ko, Andrew W. Metz, Peter Biolsi, Anton Devilliers, John Arnold, and Nelson Felix "Self-aligned blocking integration demonstration for critical sub-30-nm pitch Mx level patterning with EUV self-aligned double patterning," Journal of Micro/Nanolithography, MEMS, and MOEMS 18(1), 011002 (31 July 2018). https://doi.org/10.1117/1.JMM.18.1.011002
Received: 14 May 2018; Accepted: 15 June 2018; Published: 31 July 2018
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Cited by 6 scholarly publications.
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KEYWORDS
Etching

Extreme ultraviolet

Line edge roughness

Optical lithography

Line width roughness

Silicon

Dielectrics

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