2.1.

Wafer Reconstitution

In the chip-first wafer-level fan-out approach, wafer reconstitution takes precedence before establishing interconnections. Initially, the parent wafer is segmented into individual chiplets. These chiplets are then picked and positioned onto a 12-in. glass carrier with the assistance of a die bonding machine. Our choice of glass as a carrier is strategic, owing to its adjustable coefficient of thermal expansion, which offers the ability to control warpage, which in the realm of wafer-level packaging, if left unchecked, could lead to process-ability issues. To facilitate this, the glass surface is layered with a sacrificial release film followed by a consistent adhesive layer to bond the chiplets securely [see Figs. 2(a) and 2(b)].

Fig. 2

Process flow of the proposed package design. (a) uLED wafer dicing process, singular the wafer into individual chips, (b) the singulated chips are pick and placed on a glass carrier, forming a reconstituted wafer, (c) the reconstituted wafer is over molded, (d) then grind the mold surface until the revelation of the silicon chips, (e) TSV and RDL fabrication process are performed on the exposed chips, (f) the glass carrier is debonded, (g) singulation of the reconstituted wafer into individual packaged uLED chips, (h) the chips are picked up, and (i) then put into chip tray, ready for shipping

Posting the pick-and-place procedure, the next step is the molding process with the epoxy molding compounds (EMCs); in the realm of semiconductor packaging, the EMC serves as an encapsulation that packages the IC and provides protection from the mechanical and chemical influence of the outside. The molding process also introduces a mold flow that may push the bonded chiplets radially, which necessitates the aforementioned adhesive layer. This is succeeded by wafer-level grinding, honing down to either the chiplets’ back side or a predetermined chiplet thickness. Once this grinding phase concludes, the wafer reconstitution is complete [see Figs. 2(c) and 2(d)], resulting in what we term the “reconstituted wafer” or simply “recon wafer,” now prepared for the TSV and RDL processes.

The crux of wafer reconstitution lies in its ability to transform parent wafers of varied dimensions into a standardized 12-in. format, ensuring universal compatibility with a broad spectrum of wafer-level process machinery.

2.2.

TSV on Recon Wafer

The formation of TSVs is achieved through a series of carefully orchestrated steps. The process begins with lithography to earmark areas designated for TSVs. The photoresist was coated onto the recon wafer, then followed by the exposure to define the pattern, and finally with the assistance of the development process. The defined pattern will have its photoresist removed, with the other unexposed area still coated with the photoresist. As the photoresist is coated on the back side of the wafer, a stepper equipped with an infrared camera was used to properly align with the mark on the front side. Prior to the lithography step, we measured the post-molding die shift, and the die shifted radially from the center where the dies further from the center will have a greater shift. From Fig. 3, we can see that the maximum shifts measured are $<10\mu \mathrm{m}$, where the TSV landing pad design is $80\times 80\mu \mathrm{m}$, where the diameter of the TSV itself is $30\mu \mathrm{m}$, meaning that the TSV pattern will land within the boundary across the entire wafer. This allowed the stepper machine to use global alignment, without the need to individually align to each and every die and therefore greatly increase the throughput. This is followed by a dry etching technique, vertically penetrating the silicon until it reaches the landing pad on the active side of the chiplet. The previous lithography step ensures that the dry etching process only removes the silicon from the defined area and leaves the rest of the area protected by the photoresist intact. To ensure the purity and integrity of the TSV, a wet-dry-wet procedure is employed to purge polymer byproducts, resulting from dry etching, from both the TSV hole base and its sidewalls. Upon thorough cleaning, chemical vapor deposition (CVD) deposits a thin silicon oxide layer, serving as an insulating liner for the TSV. This liner is pivotal, averting potential current leakage.

Fig. 3

Die shift measurement result, both panels (a) and (b) showed $<10\text{-}\mu \mathrm{m}$ shift, and panel (c) identifies the direction of the shifts. Panel (d) shows the design and dimension of the TSV hole and landing pad; as long as the shift is below $25\mu \mathrm{m}$, the TSV will be able to land within the pad.

Introducing TSV dry etching on a recon wafer is a groundbreaking step, veering away from the industry’s conventional approach where chiplets were pre-equipped with TSVs within their parent wafer, pre-reconstitution. Our methodology caters to specific application wafer sizes, which traditional TSV machinery struggles to accommodate. The recon wafer emerges as a solution, making TSV formation feasible for these unconventional wafer sizes.

However, utilizing TSVs on a recon wafer is not without challenges. Early in our development, we observed adverse interactions between the TSV gas mixture and the molding compound, leading to chamber contamination. In such tainted environments, TSV dry etching could result in the formation of undesirable “TSV spikes” at the hole’s base. These spikes pose a threat as they evade coverage by the liner oxide, rendering the TSV prone to current leakage and subsequent electrical malfunctions.

To counteract this, our research led us to employ low-temperature silicon oxide as a hard mask. This effectively insulates the TSV etchant gas from the molding compound. This hard mask not only seals off the molding compound but also offers a protective shield during the wet–dry–wet cleaning process. Here, the “dry clean” denotes a plasma ashing procedure, which without the hard mask, could damage the molding compound and further contaminate the chamber. The reason why we deposited the silicon oxide under low temperature (100°C) is to avoid the undesired outgassing from the molding compound, which like another vacuum process such as TSV dry etching, will contaminate the chamber, leading to machine repair costs.

After the TSV and RDL fabrication processes, the processed recon wafer is now singulated once again to form the individually packaged chiplets. They are then picked and placed onto a tray or other packing material, now ready for the next hierarchy of the electronics assembly process [see Figs. 2(g)–2(i)].

2.3.

Finished Package

The finished package (see Fig. 4) demonstrated a significantly reduced form factor as compared with another design, which used wire bond interconnection to a laminate substrate. The current industry standard front end-of-line process necessitates that the active circuitry and the chip-to-board interconnection terminals be manufactured on the same side of the wafer, without TSVs, which will require using conventional wire bonding technique to form chip-to-board interconnection while maintaining the active side of the chip facing the environment. The wires also necessitated the need for a larger footprint beyond the uLED chip’s boundary to allow interconnection. The wafer-level-processed TSVs and RDLs removed the need for a laminate substrate and wires, the EMC no longer needed to cover the loop height of the wires to provide protection, and the absence of a laminate substrate decreased the area needed for the package. These combined reductions resulted in significantly reduced form factor in both $Z$ height and $XY$ area (97% and 42%, respectively, excluding the balls). As the targeted application is consumer AR devices, where the device appearance needs to be socially acceptable and portable, this reduction in form factor is critical to achieving this purpose, where the device is very space-constrained and electrical components need to be miniaturized to relinquish the much-needed space for the on glasses battery. The wafer-level fan-out process introduced in this paper also demonstrated consistent $>99.8\%$ electrical test yield (open/short test).

Fig. 4

Finished package of our proposed design and its features. The wire-bonded package uses the same uLED chip that is interconnected to a laminate substrate; the wires are embedded in epoxy. (a) the key compositions of the proposed wafer level package design, the combination of TSV and RDL on the uLED chip allows great reduction in form factor, (b) form factor comparison of the proposed design and a wire bonded package which contained a chip of similar size.

3.1.

Pre-reliability Assessment and Process Improvement

All electronics must undergo a reliability verification process to determine the end product’s mean time to failure and ensure that it is adequate for its intended life cycle under normal use. When we first developed the packaging structure, we subjected the packaged samples to multiple reflows.

After the assessment, all packaging structures were observed to be intact, except for the hard mask. Post multiple reflow tests (three times reflow with a peak temperature of 260°C), we observed hard mask delamination around the TSV region (see Fig. 5). Cross-section analysis revealed that the delamination propagated toward the interior of the TSV, leading to liner oxide cracks. These cracks and delamination could lead to reliability failure around the joint of the TSV and RDL, causing electrical failure. We deduced that the root cause was the brittle nature of the selected oxide material, SiN, and the stress introduced upon the SiN layer during the TSV etching process, causing the SiN material around the TSV hole to succumb to the stress and delaminate from the silicon surface, further leading to the cracking of the liner oxide around the upper neck of the TSV.

Fig. 5

Comparison of hard mask integrity after the pre-reliability assessment.

To mitigate this issue, a new material needed to be developed. We studied other CVD deposition materials and performed finite element modeling (ANSYS) to perform stress simulations using our proposed packaging structure to emulate the stress buildup around the TSV hole during our process. Package structure and process parameters were input into the model (see Fig. 6), and the results are shown in Fig. 7, indicating a 5% reduction in stress if we adopt silane oxide (leg 1) as a hard mask instead of our POR SiN (leg 2). We have also performed unit warpage simulation (Fig. 8) with the silane oxide (leg 1) and POR SiN (leg 2) as hard masks. The simulation result also points out that SiN as a hard mask does lead to a 5% greater warpage than the silane ox. The simulation results of film stress and unit warpage both indicate that the silane oxide, owing to its lower modulus, does induce smaller warpage, and therefore, a smaller warpage induced stress, making it a potential candidate to replace the SiN material to avoid the delamination issue that we observed. We fabricated another batch to empirically prove the robustness with the same pre-reliability procedure.

Fig. 6

Simulation model and input parameters.

Fig. 7

Stress simulation result of TSV region by process stage.

Fig. 8

Warpage simulation result of chip units after the RDL process.

The efficacy of switching from SiN to silane oxide was 100% effective, with no delamination or cracks observed after the multiple reflow tests. Now, the structure is fit for the formal reliability test.

3.2.

Formal Reliability Assessment

To evaluate the reliability of the designed package, three lots were fabricated and subjected to reliability assessment. After the reliability trial, the units were subjected to a light-on test to verify the chip’s functional integrity. Table 1 summarizes the reliability results, where all three lots passed the component-level reliability tests: Precon, TCT, uHAST, HTS, and HTHH. Figure 9 shows the light-on image of the packaged uLED chip, demonstrating sufficient brightness and good robustness and stability of the designed package. We further conducted SAT and cross-section analyses to ensure no abnormalities.

Table 1

Matrix of reliability items and results.

Fig. 9

Light-on image of the packaged chiplet.