Alternative patterning solutions, such as spacer-based pitch splitting, have been a cornerstone of advanced technology nodes to enable device scaling. The greatest utility comes from the ability to self-align a pitch splitting process; however, traditional spacer-based patterning techniques require the deposition and etch of multiple materials, which reduce throughput and increase manufacturing costs. Anti-spacer technology, on the other hand, enables both self-aligned pitch splitting and high throughput via a single pass track-based process. We will describe the advancement of 193i anti-spacer technology to pattern trench dimensions beyond the critical dimension resolution of single-print extreme ultraviolet lithography and the utility of combining anti-spacer patterning with litho-freeze-litho-etch to enable the formation of sub-20-nm slot contact features for a minimum tip-to-tip (T2T) cut, with a roadmap to achieve sub-12 nm. A through process performance evaluation was conducted to further the understanding of fundamental process parameters and their associated effects on anti-spacer roughness and critical dimension uniformity. Such variables include photoresist, developer optimization, and overcoat dissolution. At pitches varying from 50 to 80 nm, we have demonstrated narrow trench widths down to 11.8 nm, which corresponds to the critical T2T dimension. Through hardmask etch transfer, we observe a 56% improvement in unbiased space width roughness and pitch-walking below 0.3 nm at 60-nm pitch.
This work will describe the advancement of 193i anti-spacer technology to resolve critical trench dimensions beyond the resolution of single print EUV lithography. A through process performance evaluation will be provided for 13nm trench features from 100nm to 60nm pitch and below. A cursory review of sub-13nm feature scaling and the material factors to enable such trench dimensions will be described. The extension of 193i chemistry and associated layers to intercept EUV patternability requires an understanding of fundamental process parameters and process windows beyond standard practices. Herein, a full study of key anti-spacer parameters and their associated effects on roughness and CDU will be provided. Such variables will include resist film thickness, developer optimization and overcoat dissolution. Lastly, we will outline the ultimate scaling potential of the defined 193i anti-spacer flow and provide future avenues of development to achieve greater scaling at EUV and towards High NA EUV dimensions.
Alternative patterning solutions, such as litho-freeze-litho-etch (LFLE) and spacer-based pitch splitting, have been a cornerstone of advanced technology nodes to enable device scaling. The greatest utility comes from the ability to self-align a pitch splitting process; however, traditional spacer-based patterning techniques require the deposition and etch of multiple materials, which reduce throughput and increase manufacturing costs. Anti-spacer technology, on the other hand, enables both self-aligned pitch splitting and high throughput via a single pass track-based process. Here, we present the utility of combining a 193nm immersion anti-spacer process with LFLE to enable the formation of sub-20nm slot contact features for a minimum tip-to-tip cut, with a scaling path to achieve sub-12nm cuts.
The ever increasing pattern densities and design complexities make the tuning of optical proximity correction (OPC) recipes very challenging. One known method for tuning is genetic algorithm (GA). Previously GA has been demonstrated to fine tune OPC recipes in order to achieve better results for possible 1D and 2D geometric concerns like bridging and pinching. This method, however, did not take into account the impact of excess segmentation on downstream operations like fracturing and mask writing.
This paper introduces a general methodology to significantly reduce the number of excess edges in the OPC output, thus reducing the number of flashes generated at fracture and subsequently the write time at mask build. GA is used to reduce the degree of unwarranted segmentation while ensuring good OPC quality. An Objective Function (OF) is utilized to ensure quality convergence and process-variation (PV) plus an additional weighed factor to reduce clustered edge count.
The technique is applied to 14nm metal layer OPC recipes in order to identify excess segmentation and to produce a modified recipe that significantly reduces these segments. OPC output file sizes is shown to be reduced by 15% or more and overall edge count is shown to be reduced by 10% or more. At the same time overall quality of the OPC recipe is shown to be maintained via OPC Verification (OPCV) results.
As technology development advances into deep-sub-wavelength nodes, multiple patterning is becoming more essential to achieve the technology shrink requirements. Recently, Optical Proximity Correction (OPC) technology has proposed simultaneous correction of multiple mask-patterns to enable multiple patterning awareness during OPC correction. This is essential to prevent inter-layer hot-spots during the final pattern transfer. In state-of-art literature, multi-layer awareness is achieved using simultaneous resist-contour simulations to predict and correct for hot-spots during mask generation. However, this approach assumes a uniform etch shrink response for all patterns independent of their proximity, which isn’t sufficient for the full prevention of inter-exposure hot-spot, for example different color space violations post etch or via coverage/enclosure post etch.
In this paper, we explain the need to include the etch component during multiple patterning OPC. We also introduce a novel approach for Etch-aware simultaneous Multiple-patterning OPC, where we calibrate and verify a lumped model that includes the combined resist and etch responses. Adding this extra simulation condition during OPC is suitable for full chip processing from a computation intensity point of view. Also, using this model during OPC to predict and correct inter-exposures hot-spots is similar to previously proposed multiple-patterning OPC, yet our proposed approach more accurately corrects post-etch defects too.
Optimization of OPC recipes is not trivial due to multiple parameters that need tuning and their correlation. Usually, no standard methodologies exist for choosing the initial recipe settings, and in the keyword development phase, parameters are chosen either based on previous learning, vendor recommendations, or to resolve specific problems on particular special constructs. Such approaches fail to holistically quantify the effects of parameters on other or possible new designs, and to an extent are based on the keyword developer’s intuition. In addition, when a quick fix is needed for a new design, numerous customization statements are added to the recipe, which make it more complex.
The present work demonstrates the application of Genetic Algorithm (GA) technique for optimizing OPC recipes. GA is a search technique that mimics Darwinian natural selection and has applications in various science and engineering disciplines. In this case, GA search heuristic is applied to two problems: (a) an overall OPC recipe optimization with respect to selected parameters and, (b) application of GA to improve printing and via coverage at line end geometries. As will be demonstrated, the optimized recipe significantly reduced the number of ORC violations for case (a). For case (b) line end for various features showed significant printing and filling improvement.
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