Ms. Diana V. Nikitovich Profile

Diana V. Nikitovich

at Vinnitsa State Technical Univ

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Author

Publications (8)

Proceedings Article | 18 November 2019 Paper

Multifunctional image processor based on rank differences signals weighing-selection processing method and their simulation

Vladimir Krasilenko, Alexander Lazarev, Diana Nikitovich

Proceedings Volume 11187, 111871Q (2019) https://doi.org/10.1117/12.2538468

KEYWORDS: Image processing, Signal processing, Image filtering, Image enhancement, Signal analyzers, Electronic filtering, Analog electronics, Binary data, Image restoration, Field programmable gate arrays

Read Abstract +

A new iterative process for sorting array of signals, which differs from the known structures by uniformity and versatility, and allows direct and inverse sorting of analog or digital signal arrays was proposed in this paper. Simple relational nodes are basic elements of the proposed sorting structures. Such elements can be implemented on a different element basis, for example, on devices of selecting a maximum or minimum of two analog or digital signals, which can be implemented on CMOS current mirrors and carry out the continuous logic limited difference function. The homogeneous sorting structure on such elements implementation, consisting of two layers and a multichannel sampling and holding device was offered. Nine signals corresponding to a selection window of a matrix sensor are fed to this structure, and are sorted by five iterative steps, and at the output we receive the signals sorted by the rank, which, using the code controlled programmable multiplexer, generates an output signal, that corresponds to the selected rank. Technical parameters of such relational preprocessor were evaluated. The paper considers results of design and modeling of CL BC based on current mirrors (CM) for creating picture type image processors (IP) with matrix parallel inputsoutputs. Such sorting nodes have a number of advantages: high speed and reliability, simplicity, small power consumption, high integration level. The inclusion of an iterative node for sorting signals into a modified nonlinear IP structure makes possible to significantly simplify its design and increase the functional capabilities of such processor. The simulation results confirm the proposed approaches to the design of sorting nodes of analog signals of the iterative type. The power consumption of the processors does not exceed 2mW, the response and processing times are 10μs and can be less by an order of magnitude, the supply voltage is 1.8÷3.3V, and the operating currents are optimally in the range of 10÷20μA. The energy efficiency of the proposed preprocessor with the iterative sorting node is 25x109 operations per second per watt, which corresponds to the best technical solutions. In the work we show, that after sorting or comparative analysis of signals by levels, a promising opportunity appears to implement image processors with enhanced functionality using the new method of weighting-selecting rank differences of signals. The essence of the method is that by composing the differences of the signals ordered by rank and the upper level of their range, we can simultaneously form several resulting output signals, choosing the necessary difference signals from their set according to the control commands and weighing them additionally before the summation. We show that using this approach and the method of processing we can significantly expands the set of operations and functions for image filtering, simplifying hardware implementation of IP, especially for analog and mixed technologies. We determined set of basic executable instruction-functions of the processors, presenting the simulation results in Mathcad, PSpice OrCad and other environments. We discussed the comparative evaluation of various modifications and options for implementing processor. We analyzed the new approach for the programmable selecting function or set of functions, including the selecting the required differences between the ranks of signals and their weights. We show the results of design and modeling the proposed new FPGA-implementations of MIP. Simulation results show that processing time in such circuits does not exceed 25 nanoseconds. Circuits are simple, have low supply voltage (2.5 V), low power consumption (50mW), digital accuracy. Calculations show that in the case of using an Altera FPGA chip EP3C16F484 Cyclone III family, it is possible to implement MIP with register memory for image size of 64*64 and window 3*3 in the one chip. For the chip for 2.5V and clock frequency 200MHz the power consumption will be at the level of 200mW, and the calculation time for pixel of filters will be at the level of 25ns.

Proceedings Article | 16 October 2019 Paper

Modeling nonlinear image processing algorithms using a processor based on the sorting node

Vladimir Krasilenko, Alexander Lazarev, Diana Nikitovich

Proceedings Volume 11163, 111630I (2019) https://doi.org/10.1117/12.2535640

KEYWORDS: Signal processing, Image processing, Analog electronics, Logic, Digital signal processing, Process modeling, Nonlinear image processing, Digital image processing, Image filtering, Field programmable gate arrays

Read Abstract +

In this paper we proposed a new iterative process of sorting an array of signals, which differs from the known structures of sorting signals by uniformity, versatility, which allows direct and inverse sorting of an array of analog or digital signals. We proposed the structure of the processor based on the node that sorts the array of processed signals. Let us show the variety of the sorting node, which can be executed both iterative and pipeline–type, implementation of homogeneous sorting structure, consisting of two layers of base cells and a multichannel sampling and holding device and show that for a large number of operations and functions performed on image processing and filtering, it is necessary to sort by the signal level in the selected image window. The base cells consist of no more than 20 CMOS 1.5μm transistors, the total power consumption of the sorting node on 10 continuously logical base cells (CL BC) is 2mW, the supply voltage is 1.8÷3.3V, the range of an input photocurrent is 0.1÷24μA, the conversion cycle is 10μs. The paper considers results of design and modeling of CL BC based on current mirrors (CM) for creating picture type image processors (IP) with matrix parallel inputs-outputs. Such sorting nodes based on them have a number of advantages: high speed and reliability, simplicity, small power consumption, high integration level. The inclusion of an iterative node for sorting signals into a modified nonlinear IP structure makes it possible to significantly simplify its design and increase the functional capabilities of such processor. We evaluated the technical parameters of such a relational preprocessor. The simulation results confirm the proposed approaches to the design of sorting nodes of analog signals of the iterative type, which simplify the complexity of the nodes by an order of magnitude, ensuring their uniformity, regularity and simplicity of scaling. The power consumption of the processors does not exceed 2mW, the response and processing times are 10μs and can be less by an order of magnitude, the supply voltage is 1.8÷3.3V, and the operating currents are optimally in the range of 10÷20μA. The energy efficiency of the proposed preprocessor with the iterative sorting node is 25x10⁹ op / s • W, which corresponds to the best technical solutions. In the work we are shown, that after sorting or comparative analysis of signals by levels of selected window of image, a promising opportunity appears to implement image processors with enhanced functionality using the new method of weighting-selecting rank differences of signals. The essence of the method is that by composing the differences of the signals ordered by rank and the upper level of their range, we can simultaneously form several resulting output signals, choosing the necessary difference signals from their set according to the control commands and weighing them additionally before the summation. We are shown that using this approach and the method of processing the current window signals significantly expands the set of operations and functions for filtering images, simplifying hardware implementation of IP, especially for analog and mixed technologies. We determined the set of executed command functions by such a processor based on the sorting node, show how it can be used to separate the rank from the array of signals and analyze the new approach for the programmable selection of the required rank or the difference between the signal ranks. The use of difference-rank decomposition allows to significantly expanding the transformations range, performed over the signals of the current fragment of the processed image. We determined set of basic possible executable instruction-functions by processors based on such a proposed method, presenting the simulation results in Mathcad, PSpice OrCad and other environments. We discussed the comparative evaluation of various modifications and options for implementing processor. We analyzed the new approach for the programmable choice of its function or set of functions, including the choice of the required differences between the ranks of signals and their weights. We show the results of design and modeling the proposed new FPGA-implementations of MIP. Simulation results show that processing time in such circuits does not exceed 25 nanoseconds. Circuits are simple, have low supply voltage (2.5 V), low power consumption (50mW), digital accuracy. Calculations show that when using an Altera FPGA chip EP3C16F484 Cyclone III family, it is possible to implement MIP with register memory for image size of 64*64 and window 3*3 in the one chip. For the chip for 2.5V and clock frequency 200MHz the power consumption will be at the level of 200mW, and the calculation time for pixel of filters will be at the level of 25ns.

Proceedings Article | 16 October 2019 Paper

Rank differences of signals by weighing-selection processing method for implementation of multifunctional image processing processor

Vladimir Krasilenko, Alexander Lazarev, Diana Nikitovich

Proceedings Volume 11163, 111630J (2019) https://doi.org/10.1117/12.2538493

KEYWORDS: Signal processing, Image processing, Analog electronics, Logic, Field programmable gate arrays, Digital signal processing, Transistors, Digital electronics, Logic devices, Mirrors

Read Abstract +

In this paper, we proposed a new iterative process of sorting an array of signals, which differs from the known structures of sorting signals by uniformity, versatility, which allows direct and inverse sorting of an array of analog or digital signals. The basic elements of the proposed sorting structures are simple relational nodes. Such elements can be implemented on a different element basis, including, on devices for selecting a maximum or minimum of two analog or digital signals, which are implemented on CMOS current mirrors and carry out the limited difference function of continuous logic. We offered implementation of homogeneous sorting structure on such elements, consisting of two layers and a multichannel sampling and holding device. Nine signals corresponding to a selection window of a matrix sensor are fed to this structure, we sort them in five iterative steps, and at the output we receive the signals sorted by the rank, which, using the code controlled programmable multiplexer, generates an output signal, corresponding to the selected rank. We evaluated the technical parameters of such a relational preprocessor. The base cells consist of no more than 20 CMOS 1.5μm transistors, the total power consumption of the sorting node on 10 continuously logical base cells (CL BC) is 2mW, the supply voltage is 1.8÷3.3V, the range of an input photocurrent is 0.1÷24μA, the conversion cycle is 10μs. The paper considers results of design and modeling of CL BC based on current mirrors (CM) for creating picture type image processors (IP) with matrix parallel inputs-outputs. Such sorting nodes based on them have a number of advantages: high speed and reliability, simplicity, small power consumption, high integration level. The inclusion of an iterative node for sorting signals into a modified nonlinear IP structure makes it possible to significantly simplify its design and increase the functional capabilities of such processor. The simulation results confirm the proposed approaches to the design of sorting nodes of analog signals of the iterative type, which simplify the complexity of the nodes by an order of magnitude, ensuring their uniformity, regularity and simplicity of scaling. The power consumption of the processors does not exceed 2mW, the response and processing times are 10μs and can be less by an order of magnitude, the supply voltage is 1.8÷3.3V, and the operating currents are optimally in the range of 10÷20μA. The energy efficiency of the proposed preprocessor with the iterative sorting node is 25x10⁹ op / s•W, which corresponds to the best technical solutions. In the work we are shown, that after sorting or comparative analysis of signals by levels of selected window of image, a promising opportunity appears to implement image processors with enhanced functionality using the new method of weighting-selecting rank differences of signals. The essence of the method is that by composing the differences of the signals ordered by rank and the upper level of their range, we can simultaneously form several resulting output signals, choosing the necessary difference signals from their set according to the control commands and weighing them additionally before the summation. We are shown that using this approach and the method of processing the current window signals significantly expands the set of operations and functions for filtering images, simplifying hardware implementation of IP, especially for analog and mixed technologies. We determined set of basic possible executable instruction-functions by processors based on such a proposed method, presenting the simulation results in Mathcad, PSpice OrCad and other environments. We discussed the comparative evaluation of various modifications and options for implementing processor. We analyzed the new approach for the programmable choice of its function or set of functions, including the choice of the required differences between the ranks of signals and their weights. We show the results of design and modeling the proposed new FPGA-implementations of MIP. Simulation results show that processing time in such circuits does not exceed 25 nanoseconds. Circuits are simple, have low supply voltage (2.5 V), low power consumption (50mW), digital accuracy. Calculations show that when using an Altera FPGA chip EP3C16F484 Cyclone III family, it is possible to implement MIP with register memory for image size of 64*64 and window 3*3 in the one chip. For the chip for 2.5V and clock frequency 200MHz the power consumption will be at the level of 200mW, and the calculation time for pixel of filters will be at the level of 25ns.

Proceedings Article | 14 May 2019 Paper

Design of neuron-calculators for the normalized equivalence of two matrix arrays based on FPGA for self-learning equivalently convolutional neural networks (SLE_CNNs)

Vladimir Krasilenko, Alexander Lazarev, Diana Nikitovich

Proceedings Volume 10996, 109960P (2019) https://doi.org/10.1117/12.2518206

KEYWORDS: Neurons, Image processing, Field programmable gate arrays, Neural networks, Image filtering, Convolutional neural networks

Read Abstract +

First, in the introduction, we will show the urgent need to create neuron-calculators (NCs) for the normalized equivalence of two matrix arrays for self-learning equivalently-convolutional neural networks (SLE_CNNs), video processors for parallel image processing with enhanced functionality. Consider promising areas of application of such single and multichannel neuron-calculators as high-precision, high-speed and high-performance accelerators for hardware systems and architectures for recognition, classification, image categorization, in particular for 2D-image space-invariant associative memory structures, SLE_CNNs based on the equivalence paradigm. Next, we will consider and analyze the theoretical foundations, the mathematical apparatus of matrix and continuous logic, and their basic operations, show their functional completeness, evaluate their advantages and prospects for application in the design of biologically inspired devices and systems for processing and analyzing signal arrays. We will show that some functions of continuous logic, including operations of normalized equivalence of vector and matrix signals, operation of the bounded difference of continuous logic, are the powerful basis for designing advanced accelerator calculators, microcells for hybrid (mixed) analog-to-digital transformations, comparisons and calculations of characteristics. Next, we will consider in more detail the design and simulation aspects of such digital neuron-calculators for the normalized equivalence of two matrix arrays based on FPGA, including their various modifications, depending on the dimension and the number of compared arrays. We will propose our approach for calculation of the normalized equivalence functions comparing current fragments of images and filters with dimensions 3×3, 7×7, 15×15, and others. The project is executed on FPGA ALTERA MAXII. The simulation was done with Intel Quartus Prime 17 and showed that in a single chip it is possible to place four parallel working neuron calculators processing 4 filters with a size of 15×15. The approximate processing time is less than 5μs. Power consumption is 50mW for supply voltage of 2.5V and clock frequency equals to 50MHz. We will also consider modifications that improve performance for different filter size. We show the results of modeling the proposed new implementations of NCs, we estimates and compare them.

Proceedings Article | 11 April 2019 Paper

Design and simulation of image nonlinear processing relational preprocessor based on iterational sorting node

Vladimir Krasilenko, Alexander Lazarev, Diana Nikitovich

Proceedings Volume 11028, 110282X (2019) https://doi.org/10.1117/12.2524114

KEYWORDS: Image processing, Analog electronics, Logic, Signal processing, Logic devices, Transistors, Sensors, Mirrors, Optoelectronics, Evolutionary algorithms

Read Abstract +

In this paper, we propose a new iterative process of sorting an array of signals, which differs from the known structures of sorting signals by uniformity, versatility, which allows direct and inverse sorting of an array of analog or digital signals. The basic elements of the proposed sorting structures are simple relational nodes for analogue signals from sensor devices and cameras. Such elements can be implemented on a different element basis, including, on devices for selecting a maximum or minimum of two analog or digital signals, which are implemented, in one of the variants, on CMOS current mirrors and carry out the function of continuous logic limited difference. We offer optoelectronic implementation of such basic relational element and a homogeneous sorting structure on such elements, consisting of two layers and a multichannel sampling and holding device. Nine signals corresponding to a selection window of a matrix sensor are fed to this structure, we sort them in five iterative steps, and at the output we receive the signals sorted by the rank, which, using the code controlled programmable multiplexer, generates an output signal, corresponding to the selected rank. We evaluate the technical parameters of such a relational preprocessor for nonlinear signal processing in image processors, sorting networks, multichannel parallel type sensor, processing, and encoding systems. The base cells consist of no more than 20 CMOS 1.5μm transistors, the total power consumption of the sorting node on 10 continuously logical base cells (CL BC) is 2mW, the supply voltage is 1.8÷3.3V, the range of an input photocurrent is 0.1÷24μA, the conversion cycle is 10μs, but can be improved by selecting other transistors and some modifications of the circuits. Such mixed analog processor is modeled in PSpice OrCad. The paper considers results of design and modeling of CL BC based on photosensitive cells with an extended electronic circuit and current mirrors (CM) with functions of preliminary subsequent analogue processing for creating picture type image processors (IP) with matrix parallel inputs-outputs. Such BCs and sorting nodes based on them have a number of advantages: high speed and reliability, simplicity, small power consumption, high integration level. We consider CL BC for methods of selection and rank preprocessing. In contrast to our previous works here we will dwell more on analogue preprocessing schemes for signals of neighboring cells. Let us show how the introduction of iterative sorting nodes extends the range of functions performed by the IPs. Examples of image processing with proposed preprocessor are simulated in MathCad and show the field of application of such coprocessors and new prospects for realization of linear and matrix photo-electronic structures with matrix operands. The essential difference is that the structure is iterative and allows to significantly reducing hardware costs in comparison with other hardware implementations of sorting networks. We discuss some aspects of possible rules and principles of learning and programmable configuration for the required function, relational work, and the implementation of hardware blocks for modifying such processors.

Proceedings Article | 7 September 2018 Paper

Design and simulation of array cells for image intensity transformation and coding used in mixed image processors and neural networks

Vladimir Krasilenko, Alexander Lazarev, Diana Nikitovich

Proceedings Volume 10751, 1075119 (2018) https://doi.org/10.1117/12.2322655

KEYWORDS: Image processing, Mirrors, Transistors, Device simulation, Neural networks, Analog electronics, Mathematical modeling, Imaging arrays, Neurons

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The paper considers results of design and simulation of continuously logical cells (CLC) based on current mirrors (CM) with functions of preliminary analogue processing for image intensity transformation and coding for construction of mixed image processors (IP) and neural networks (NN). For such IP and NN with vector or matrix parallel inputsoutputs, it is needed active basic photosensitive cells with an extended electronic circuit, which are considered in paper. Such CLC has a number of advantages: high speed and reliability, simplicity, small power consumption, high integration level for linear and matrix structures. We show design of CLC variants for photocurrents transformation and coding and their various possible implementations and simulations. The basic element of such cells is a scheme that implements the operation of a bounded difference of continuous logic. Using a set of such circuits implemented on traditional CMOS technology, we consider generalized decomposition and other methods for designing cells for nonlinear conversion of the photocurrent intensity, which makes it easy to realize the required nonlinear conversion function. Selection of the appropriate parameters, which can be specified as constructive constants or as parameters for external control, allows changing type of synthesized functions. We also consider the applications of such parallel matrix arrays for the creation of advanced IP and NN. We show the need for various types of converting and coding the photocurrents intensity in such parallel systems and sensory devices, especially for the implementation of various types of activation functions in the hardware implementations of neural networks. Such cells consist of several dozen CMOS transistors, have low power supply voltage (1.8 ÷ 3.3V), the range of an input photocurrent is 0.1÷24μA, the transformation time is less than 1 μs, low power consumption (microwatts). We also consider the cells for ADC after the intensity conversion. Each channel consists of several digital-analog cells (DC). The amount of DC is not exclusive to the number of digits of the formed code, and for an iteration type, only one cell of DC, complemented by the device of selection and holding (SHD), is required. One channel of ADC with iteration is based on one DC and SHD, and it has only 35 CMOS transistors. The general power consumption of the ADC with iteration is only 50÷100μW, if the maximum input current is 4μA. The ADCs with 6-8 bit binary or Gray codes have good dynamic characteristics (frequency of digitization even for 1.5μm CMOS-technologies is 10MHz and more). In such ADCs, easily parallel code can be realized. The circuits and the simulation results of their design with OrCAD are shown. The CLC and ADC on current mirrors open new prospects for realization of linear and matrix IP and NN with MIMO-operands.

Proceedings Article | 21 May 2018 Paper

Design and simulation of optoelectronic neuron equivalentors as hardware accelerators of self-learning equivalent convolutional neural structures (SLECNS)

Vladimir Krasilenko, Alexander Lazarev, Diana Nikitovich

Proceedings Volume 10689, 106890C (2018) https://doi.org/10.1117/12.2316352

KEYWORDS: Analog electronics, Neurons, Neural networks, Image processing, Convolution, Process modeling, Nonlinear filtering, Systems modeling

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In the paper, we consider the urgent need to create highly efficient hardware accelerators for machine learning algorithms, including convolutional and deep neural networks (CNN and DNNS), for associative memory models, clustering, and pattern recognition. These algorithms usually include a large number of multiply-accumulate (and the like) operations. We show a brief overview of our related works the advantages of the equivalent models (EM) for describing and designing neural networks and recognizing bio-inspired systems. The capacity of NN on the basis of EM and of its modifications, including auto-and hetero-associative memories for 2D images, is in several times quantity of neurons. Such neuroparadigms are very perspective for processing, clustering, recognition, storing large size and strongly correlated and highly noised images. They are also very promising for solving the problem of creating machine uncontrolled learning. And since the basic operational functional nodes of EM are such vector-matrix or matrix-tensor procedures with continuous-logical operations as: normalized vector operations "equivalence", "nonequivalence", "autoequivalence", "auto-nonequivalence", we consider in this paper new conceptual approaches to the design of full-scale arrays of such neuron-equivalentors (NEs) with extended functionality, including different activation functions. Our approach is based on the use of analog and mixed (with special coding) methods for implementing the required operations, building NEs (with number of synapsis from 8 up to 128 and more) and their base cells, nodes based on photosensitive elements and CMOS current mirrors. We show the results of modeling the proposed new modularscalable implementations of NEs, we estimates and compare them. Simulation results show that processing time in such circuits does not exceed units of micro seconds, and for some variants 50-100 nanoseconds. Circuits are simple, have low supply voltage (1.5 – 3.3 V), low power consumption (milliwatts), low levels of input signals (microwatts), integrated construction, satisfy the problem of interconnections and cascading. Signals at the output of such neurons can be both digital and analog, or hybrid, and also with two complement outputs. They realize principle of dualism which gives a number of advantages of such complement dual NEs.

Proceedings Article | 8 March 2018 Paper

Modeling of biologically motivated self-learning equivalent-convolutional recurrent-multilayer neural structures (BLM_SL_EC_RMNS) for image fragments clustering and recognition

Vladimir Krasilenko, Alexander Lazarev, Diana Nikitovich

Proceedings Volume 10609, 106091D (2018) https://doi.org/10.1117/12.2285797

KEYWORDS: Image filtering, Optical filters, Image processing, Convolution, Neurons, Image restoration, Mathematical modeling, Nonlinear filtering, Image analysis, Machine learning

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The biologically-motivated self-learning equivalence-convolutional recurrent-multilayer neural structures (BLM_SL_EC_RMNS) for fragments images clustering and recognition will be discussed. We shall consider these neural structures and their spatial-invariant equivalental models (SIEMs) based on proposed equivalent two-dimensional functions of image similarity and the corresponding matrix-matrix (or tensor) procedures using as basic operations of continuous logic and nonlinear processing. These SIEMs can simply describe the signals processing during the all training and recognition stages and they are suitable for unipolar-coding multilevel signals. The clustering efficiency in such models and their implementation depends on the discriminant properties of neural elements of hidden layers. Therefore, the main models and architecture parameters and characteristics depends on the applied types of non-linear processing and function used for image comparison or for adaptive-equivalent weighing of input patterns. We show that these SL_EC_RMNSs have several advantages, such as the self-study and self-identification of features and signs of the similarity of fragments, ability to clustering and recognize of image fragments with best efficiency and strong mutual correlation. The proposed combined with learning-recognition clustering method of fragments with regard to their structural features is suitable not only for binary, but also color images and combines self-learning and the formation of weight clustered matrix-patterns. Its model is constructed and designed on the basis of recursively continuous logic and nonlinear processing algorithms and to k-average method or method the winner takes all (WTA). The experimental results confirmed that fragments with a large numbers of elements may be clustered. For the first time the possibility of generalization of these models for space invariant case is shown. The experiment for an images of different dimensions (a reference array) and fragments with diferent dimensions for clustering is carried out. The experiments, using the software environment Mathcad showed that the proposed method is universal, has a significant convergence, the small number of iterations is easily, displayed on the matrix structure, and confirmed its prospects. Thus, to understand the mechanisms of self-learning equivalence-convolutional clustering, accompanying her to the competitive processes in neurons, and the neural auto-encoding-decoding and recognition principles with the use of self-learning cluster patterns is very important which used the algorithm and the principles of non-linear processing of two-dimensional spatial functions of images comparison. The experimental results show that such models can be successfully used for auto- and hetero-associative recognition. Also they can be used to explain some mechanisms, known as "the reinforcementinhibition concept". Also we demonstrate a real model experiments, which confirm that the nonlinear processing by equivalent function allow to determine the neuron-winners and customize the weight matrix. At the end of the report, we will show how to use the obtained results and to propose new more efficient hardware architecture of SL_EC_RMNS based on matrix-tensor multipliers. Also we estimate the parameters and performance of such architectures.

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