In a conventional lithography process with Al film structure, the photo resist pattern is removed by two methods: wet
etch or wet etch combine with dry strip process.
There were some problems in these kinds of processes. Pattern collapsed after wet etch process due to the photo resist
(PR) adhesion capability reduced. Contact angle can be the index to measure the adhesion capability.
So as to prevent the pattern collapsed issue, a high-temperature plasma treatment step was added after wet etch. But it
induces another issue. IC devices fabrication in Al interconnect process, 0.5wt% Cu is generally used in Al film
deposition for better Al electron migration performance. The high-temperature Plasma with high potentiality of CuAl2
precipitation, which will form a residue cause the metal line bridge induce yield loss.
In this paper, we modify the rework procedure and lower the plasma processing temperature to the "room
temperature" to prevent the pattern collapsed issue and the CuAl2 precipitation.
The modified rework procedure is not only improved the defect, WAT and yield, but also reduce the cycle time of
resist remove process.
Dual damascene technique has been widely applied to IC device fabrication in copper interconnect
process. For traditional via-first dual damascene application, a fill material is first employed to fill via to protect
over-etching and punch-through of the bottom barrier layer during the trench-etch process. Etch-back process is then
applied to remove excess overfill thickness and maintain a greater planar topography. To get better CD control, a thin
organic BARC is finally coated to reduce reflectivity for trench patterning but not in this study. It is a multi-step and
costly dual damascene process. In this study, a new gap-filling BARC material with good via fill and light
absorption features was adopted to explore the via-first dual damascene process by skipping etch-back and BARC
coating steps. The results show not only the reduction of process cycle time and cost saving but also the CP yield
improvement based on data from pilot production of 0.11/0.13 μm logic device.
As the IC product scribe line of logic 90nm (L90) technology shrinks from 80µm to 62μm, the wafer
quality (W.Q.), will become weak and less distinguishable during the subsequent ASML scanner stepper's
photo mask aligning. Many wafers having photo mask aligning errors will eventually lead to wafer
scrapping. In order to improve the photo alignment signal (W.Q.) acquired from the relatively smaller 62μm
scribe-line's alignment mark while proceeding with the VIA layer photo aligning directly to its previous metal
layer, it is found that removing the TiN hard mask (H.M.) just above the previous inter-metal dielectric (IMD)
and alignment mark area can help the deep ultra-violet (DUV) 193nm wavelength ASML scanner stepper
successfully acquires a better alignment signal and alignment accuracy (A.A.).
However, due to copper (Cu) residues and CMP dishing after metal copper CMP, it has been found
that both large area "half size open" and "full size open" approaches for TiN removing in the scribe-line
alignment area can not be used. Hence, for safer photolithography aligning margin the "sizing + 0.25μm"
mark on the scribe line's photo alignment area is suggested for better signal acquiring, whose experimental
results in UMC shows that around 90% of the alignment signal (W.Q.) can be verified. The alignment
accuracy (A.A.) can also be improved through using this technique and is accurate enough as compared to the
conventional scanner alignment method used for above 0.13μm generation technology.
RRC (Reducing resist consumption) coating is widely used to reduce photo resist consumption. By using solvent to
pre-wet the wafer surface, photo resist can be coated on wafer easier than normal coating method. But it also can be the
source of defects. In this study, we found that RRC solvent will induce micro-bubble and cause defects. Different
methods had been tried to solve this kind of micro-bubble defects. Results showed that micro-bubble defects can be
found when the wafer is static during RRC solvent dispense. And the defect map was a ring shape. The diameter of the
rings depended on the RRC solvent dispense amount. Non micro-bubble defect was found, if wafer was spinning during
RRC solvent dispense.
A thin FinFET bulk Si-fin body structure has been successfully fabricated upon bulk-Si wafers through
using 193nm scanner lithography and a composite hard mask etching technique. First, a 100Å-thick
buffer SiO2 layer was thermally grown upon the bulk silicon layer and subsequently a 1200Å-thick SiNx
layer and a 1000Å-thick TEOS SiO2 hard mask layer was chemically vapor deposited to form a
composite hard mask structure of buffer-SiO2/SiNx/TEOS. Second, both 1050Å-thick BARC and
2650Å-thick photoresist (P/R) were coated and a 193nm scanner lithography tool was used for the Si-fin
body layout patterning under relatively high exposure energy. This achieves the ADI (after develop
inspection) of 80nm from the original as-drawn Si-fin layout of 110nm. Then, a deep sub-micron
plasma etcher was used for an aggressive P/R and BARC trimming down processing and both the
capping TEOS and CVD-SiNx with its underlying buffer oxide layers were subsequently etched in other
etching plasma chambers, respectively. Resultantly, the AMI (after mask inspection) can reach 60nm.
Subsequently, both the P/R and BARC were removed with a nominal plasma ashing as well as a RCA
cleaning for the final sub-micron Si-fin plasma etching. Eventually, a 60nm-width and 400nm-height
bulk Si-fin body structure can be successfully etched out after a fixed time-mode silicon plasma etching.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.