Dr. Emmanuel Dupuy Profile

Dr. Emmanuel Dupuy

at imec

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Publications (6)

Proceedings Article | 1 May 2023 Presentation + Paper

Middle-of-line plasma dry etch challenges for CFET integration

D. Radisic, M. Hosseini, H. Mertens, D. Zhou, V. Vega Gonzalez, S. Wang, B. Chan, D. Batuk, E. Dupuy, Z. Tao, E. Dentoni Litta, N. Horiguchi

Proceedings Volume 12499, 1249909 (2023) https://doi.org/10.1117/12.2659095

KEYWORDS: Etching, Optical lithography, Lithography, Plasma etching, Plasma, Dry etching, Critical dimension metrology, Dielectrics

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In this paper, middle-of-line (MOL) plasma etch development results for the monolithic CFET integration with nanosheet devices using scaling-relevant test vehicle (CPP48nm) are presented. Several critical MOL patterning steps are addressed, with the focus on the patterning of the trenches (M0) for contacting to the bottom and top devices. The patterning of M0A consists of SiO₂ dielectric and thin SiN liner etch landing on epitaxial source drain (S/D). The critical M0 etch requirement is preserving the SiN gate spacer to avoid shorting between S/D and gate. Due to no-gate plug implementation in the process flow, the etch development must rely on very challenging, patterning the small critical dimension (CD) contacts to create enough dielectric barrier between the metal contact and the gate, and preferably, also very challenging, self-alignment to the thin gate spacer. The dependance of the M0 CD and the etch depth is accessed by using the range of the EUV lithography conditions and evaluating the maximum etch depth of the trench as a function of the printed CD. The minimum trench CD achieved on the bottom of the trench is ~ 13nm, and the minimum top CD in the range of ~ 16nm, with the evident etch non-uniformity observed in the etch depth. The trend of larger contact CD resulting in the deeper etch and process uniformity improvement is observed. Etch depth larger than 100nm is achieved when top M0 CD is >20nm. The option with the SiN liner deposition followed by SiN liner etch (spacer formation) post- M0 SiO₂ is developed. This patterning sequence consists of SiO₂ etch stopping on the thin SiN (over S/D) followed by additional SiN deposition and finally etching of the deposited SiN liner as well as SiN liner covering S/D. The option with SiN spacer formation minimizes the risk of short to the gate, due to extra SiN dielectric film protecting the gate. In addition, we present the results for another critical MOL patterning step, i.e., HAR metal recess post M0 metallization (AR~11)

Proceedings Article | 25 May 2022 Presentation + Paper

Buried power rail integration for CMOS scaling beyond the 3 nm node

A. Gupta, Z. Tao, D. Radisic, H. Mertens, O. Varela Pedreira, S. Demuynck, J. Bömmels, K. Devriendt, N. Heylen, S. Wang, K. Kenis, L. Teugels, F. Sebaai, C. Lorant, N. Jourdan, B. Chan, S. Subramanian, F. Schleicher, A. Peter, N. Rassoul, Y. Siew, B. Briggs, D. Zhou, E. Rosseel, E. Capogreco, G. Mannaert, A. Sepúlveda, E. Dupuy, K. Vandersmissen, B. Chehab, G. Murdoch, E. Altamirano Sanchez, S. Biesemans, Zs. Tőkei, E. Dentoni Litta, N. Horiguchi

Proceedings Volume 12056, 120560B (2022) https://doi.org/10.1117/12.2615641

KEYWORDS: Ruthenium, Metals, Molybdenum, Etching, Tungsten, Front end of line, Chemical mechanical planarization, Silicon

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Proceedings Article | 23 March 2020 Presentation + Paper

FEOL dry etch process challenges of ultimate FinFET scaling and next generation device architectures beyond N3

Z. Tao, L. Zhang, E. Dupuy, B. T. Chan, E. Altamirano-Sanchez, F. Lazzarino

Proceedings Volume 11329, 113290O (2020) https://doi.org/10.1117/12.2552022

KEYWORDS: Etching, Optical lithography, Silicon, Fin field effect transistors, Front end of line, Dry etching, Field effect transistors, Gallium arsenide, Plasma etching, Nanowires

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FinFETs have demonstrated significant performance improvement compared to planar devices, because of its superior short channel control and higher driving capability at a much smaller footprint. It has become the mainstream technology in CMOS industry since N20 node onward. Contact Poly Pitch (CPP) scaling used to be the main driving force in extending Moore’s law. However, severe limitations are foreseen from N3 node in terms of electrical performance, process requirements and manufacturing complexity. At N3 node, both fin and gate pitches are expected to reach their ultimate values, respectively 21 nm and 42 nm. Therefore, complex plasma etching processes using advanced plasma pulsing modes or atomic layer etching (ALE) are deployed to achieve high aspect ratio patterning capability with a detrimental effect on both process control and throughput. As an alternative, device architecture innovation will become the main scaling driving force for N3 node and beyond. 2D scaling like horizontal Gate-All-Around (GAA) devices, such as nanosheet (NS) and forksheet (FS) have demonstrated the potential for further device performance improvement [1,2]. The major NS patterning challenges are the SiGe lateral etch in the Si/SiGe superlattice stack and severe depth micro-loading due to the etch rate difference of SiGe and Si. In addition, 3D hybrid device architectures like Complementary FET (CFET) and Surrounding-Gate-Transistors (SGT) are proposed as revolutionary innovations to scale the devices in the vertical direction. For CFET devices, the N/P separation is moved to the vertical direction by stacking nMOS on top of pMOS or vice versa to achieve aggressive device scaling. This requires extremely high aspect ratio fin and gate patterning compared to horizontal-GAA NS devices. For SGT device, the channel is switched to the vertical direction, which can decouple the Gate length (Lg) from CPP scaling and eliminate the diffusion break to deeply scale the cell size. High aspect ratio vertical nanowire (NW) and direct metal gate etching with tight pitch are the new FEOL patterning challenges for the fabrication of SGT vertical devices.

Proceedings Article | 17 March 2015 Paper

Spectral analysis of the line-width and line-edge roughness transfer during self-aligned double patterning approach

Emmanuel Dupuy, E. Pargon, M. Fouchier, H. Grampeix, J. Pradelles, M. Darnon, P. Pimenta-Barros, S. Barnola, O. Joubert

Proceedings Volume 9428, 94280B (2015) https://doi.org/10.1117/12.2085812

KEYWORDS: Line edge roughness, Line width roughness, Plasma, Etching, Critical dimension metrology, Plasma etching, Silicon, Oxygen, Photoresist processing, Neodymium

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Proceedings Article | 28 May 2013 Paper

The photonic nanowire: an emerging platform for highly efficient single-photon sources for quantum information applications

Niels Gregersen, Mathieu Munsch, Nitin Malik, Joël Bleuse, Emmanuel Dupuy, Adrien Delga, Jesper Mørk, Jean-Michel Gérard, Julien Claudon

Proceedings Volume 8749, 87490W (2013) https://doi.org/10.1117/12.2020622

KEYWORDS: Surface plasmons, Mirrors, Quantum information, Quantum efficiency, Gaussian beams, Interfaces, Metals, Semiconductors, Nanowires, Photonic nanostructures

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Proceedings Article | 14 March 2013 Paper

A photonic nanowire trumpet for interfacing a quantum dot and a Gaussian free-space mode

Niels Gregersen, Mathieu Munsch, Nitin Malik, Joël Bleuse, Emmanuel Dupuy, Adrien Delga, Jesper Mørk, Jean-Michel Gérard, Julien Claudon

Proceedings Volume 8619, 86190Y (2013) https://doi.org/10.1117/12.2004449

KEYWORDS: Quantum dots, Gaussian beams, Surface plasmons, Mirrors, Quantum efficiency, Interfaces, Semiconductors, Gallium arsenide, Nanowires, Photonic nanostructures

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Showing 5 of 6 publications

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