Dr. Frank E. Gennari Profile

Dr. Frank E. Gennari

Senior Member of Consulting Staff at Cadence Design Systems Inc

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Author

Publications (20)

Proceedings Article | 22 February 2021 Poster + Paper

Fast, high-capacity critical area analysis (CAA) with advanced FINFET defectivity calculation

Xiaoyuan Qi, Atul Chittora, Aaron Sinnott, Binod Kumar G. Nair, Shobhit Malik, Jeffrey Nelson, Jac Condella, Jonathan Fales, Rwik Sengupta, Ya-Chieh Lai, Frank Gennari, Philippe Hurat

Proceedings Volume 11614, 1161413 (2021) https://doi.org/10.1117/12.2583515

KEYWORDS: Fin field effect transistors, Transistors, Semiconductors, High volume manufacturing, Databases, Data modeling

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Proceedings Article | 23 March 2020 Presentation + Paper

Jaehwan Kim, Jin Kim, Byungchul Shin, Sangah Lee, Jae-Hyun Kang, Joong-Won Jeon, Piyush Pathak, Jac Condella, Frank Gennari, Philippe Hurat, Ya-Chieh Lai

Proceedings Volume 11328, 113280I (2020) https://doi.org/10.1117/12.2551970

KEYWORDS: Metals, Design for manufacturing, Chemical mechanical planarization, Silicon, Reliability, Optical proximity correction, Semiconducting wafers, Extreme ultraviolet lithography, Manufacturing, Yield improvement

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Proceedings Article | 4 April 2019 Presentation + Paper

A novel design-for-yield solution based on interconnect level layout improvements at 7nm technology node

Jaehwan Kim, Sangah Lee, Byungchul Shin, J. Jeon, Jin Kim, B. M. Kim, Jae-Hyun Kang, Seungweon Paek, Piyush Pathak, Frank Gennari, Philippe Hurat, Ya-Chieh Lai

Proceedings Volume 10962, 1096204 (2019) https://doi.org/10.1117/12.2514896

KEYWORDS: Computer aided design, Metals, Resolution enhancement technologies, Optical lithography, CMOS technology, Extreme ultraviolet, Extreme ultraviolet lithography, Lithography, Double patterning technology, Manufacturing

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Proceedings Article | 20 March 2019 Presentation + Paper

Hotspot detection using squish-net

Haoyu Yang, Piyush Pathak, Frank Gennari, Ya-Chieh Lai, Bei Yu

Proceedings Volume 10962, 109620S (2019) https://doi.org/10.1117/12.2515172

KEYWORDS: Machine learning, Neural networks, Design for manufacturing, Convolution, Model-based design, Charge-coupled devices, Metals, Semiconductor manufacturing, Artificial intelligence, Convolutional neural networks

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Proceedings Article | 18 March 2019 Presentation

Pattern-aware diagnostics: using high-performance pattern analysis to identify defect root cause (Conference Presentation)

Jason Cain, Abdullah Yassine, Moutaz Fakhry, Piyush Pathak, Jeffrey Nelson, Frank Gennari, Ya-Chieh Lai

Proceedings Volume 10962, 1096209 (2019) https://doi.org/10.1117/12.2516571

KEYWORDS: Diagnostics, Failure analysis, Machine learning, Feature extraction, Inspection, High volume manufacturing, Silicon

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Proceedings Article | 10 April 2018 Presentation + Paper

Applying machine learning to pattern analysis for automated in-design layout optimization

Jason Cain, Moutaz Fakhry, Piyush Pathak, Jason Sweis, Frank Gennari, Ya-Chieh Lai

Proceedings Volume 10588, 1058805 (2018) https://doi.org/10.1117/12.2299492

KEYWORDS: Machine learning, Data modeling, Model-based design, Testing and analysis, Manufacturing, Lithography, Design for manufacturing, Feature extraction

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Proceedings Article | 30 March 2017 Paper

Pattern-based analytics to estimate and track yield risk of designs down to 7nm

Jason Cain, Moutaz Fakhry, Piyush Pathak, Jason Sweis, Frank Gennari, Ya-Chieh Lai

Proceedings Volume 10148, 1014805 (2017) https://doi.org/10.1117/12.2262363

KEYWORDS: Databases, Process modeling, Analytics, Design for manufacturability, Design for manufacturing, Yield improvement, Silicon, Model-based design, Statistical analysis, Product engineering, Metals, Optical lithography, Charge-coupled devices, Computer simulations, Manufacturing, Logic, Optical proximity correction, Digital electronics

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Proceedings Article | 16 March 2016 Paper

Methodology to extract, data mine and score geometric constructs from physical design layouts for analysis and applications in semiconductor manufacturing

Piyush Pathak, Karthik Krishnamoorthy, Wei-Long Wang, Ya-Chieh Lai, Frank Gennari, Shikha Somani, Bob Pack, Uwe Paul Schroeder, Fadi Batarseh, Jaime Bravo, Jason Sweis, Philippe Hurat, Sriram Madhavan

Proceedings Volume 9781, 978109 (2016) https://doi.org/10.1117/12.2220145

KEYWORDS: Design for manufacturing, Mining, Design for manufacturability, Manufacturing, Semiconductor manufacturing, Image classification, Machine learning, Optical proximity correction, Lithography, Semiconductors, Metals, Databases, Charge-coupled devices, Silicon, Data mining, Computer simulations

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Proceedings Article | 16 March 2016 Paper

Methodology for analyzing and quantifying design style changes and complexity using topological patterns

Jason Cain, Ya-Chieh Lai, Frank Gennari, Jason Sweis

Proceedings Volume 9781, 978108 (2016) https://doi.org/10.1117/12.2220021

KEYWORDS: Metals, Databases, Digital electronics, Manufacturing, Raster graphics, Logic, System on a chip, Optical lithography, Optical proximity correction, Product engineering

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Proceedings Article | 28 March 2014 Paper

Systematic physical verification with topological patterns

Vito Dai, Ya-Chieh Lai, Frank Gennari, Edward Teoh, Luigi Capodieci

Proceedings Volume 9053, 905304 (2014) https://doi.org/10.1117/12.2046709

KEYWORDS: Raster graphics, Manufacturing, Metals, Electronic design automation, Profiling, Design for manufacturability, Design for manufacturing, Optical alignment, Multilayers, Databases

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Design rule checks (DRC) are the industry workhorse for constraining design to ensure both physical and electrical manufacturability. Where DRCs fail to fully capture the concept of manufacturability, pattern-based approaches, such as DRC Plus, fill the gap using a library of patterns to capture and identify problematic 2D configurations. Today, both a DRC deck and a pattern matching deck may be found in advanced node process development kits. Major electronic design automation (EDA) vendors offer both DRC and pattern matching solutions for physical verification; in fact, both are frequently integrated into the same physical verification tool.

In physical verification, DRCs represent dimensional constraints relating directly to process limitations. On the other hand, patterns represent the 2D placement of surrounding geometries that can introduce systematic process effects. It is possible to combine both DRCs and patterns in a single topological pattern representation. A topological pattern has two separate components: a bitmap representing the placement and alignment of polygon edges, and a vector of dimensional constraints. The topological pattern is unique and unambiguous; there is no code to write, and no two different ways to represent the same physical structure. Furthermore, markers aligned to the pattern can be generated to designate specific layout optimizations for improving manufacturability.

In this paper, we describe how to do systematic physical verification with just topological patterns. Common mappings between traditional design rules and topological pattern rules are presented. We describe techniques that can be used during the development of a topological rule deck such as: taking constraints defined on one rule, and systematically projecting it onto other related rules; systematically separating a single rule into two or more rules, when the single rule is not sufficient to capture manufacturability constraints; creating test layout which represents the corners of what is allowed, or not allowed by a rule; improving manufacturability by systematically changing certain patterns; and quantifying how a design uses design rules. Performance of topological pattern search is demonstrated to be production full-chip capable.

Proceedings Article | 28 March 2014 Paper

Systematic data mining using a pattern database to accelerate yield ramp

Edward Teoh, Vito Dai, Luigi Capodieci, Ya-Chieh Lai, Frank Gennari

Proceedings Volume 9053, 905306 (2014) https://doi.org/10.1117/12.2047307

KEYWORDS: Manufacturing, Image classification, Raster graphics, Databases, Image processing, Optical proximity correction, Silicon, Data mining, Tolerancing, Lithography

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Pattern-based approaches to physical verification, such as DRC Plus, which use a library of patterns to identify problematic 2D configurations, have been proven to be effective in capturing the concept of manufacturability where traditional DRC fails. As the industry moves to advanced technology nodes, the manufacturing process window tightens and the number of patterns continues to rapidly increase. This increase in patterns brings about challenges in identifying, organizing, and carrying forward the learning of each pattern from test chip designs to first product and then to multiple product variants. This learning includes results from printability simulation, defect scans and physical failure analysis, which are important for accelerating yield ramp.

Using pattern classification technology and a relational database, GLOBALFOUNDRIES has constructed a pattern database (PDB) of more than one million potential yield detractor patterns. In PDB, 2D geometries are clustered based on similarity criteria, such as radius and edge tolerance. Each cluster is assigned a representative pattern and a unique identifier (ID). This ID is then used as a persistent reference for linking together information such as the failure mechanism of the patterns, the process condition where the pattern is likely to fail and the number of occurrences of the pattern in a design. Patterns and their associated information are used to populate DRC Plus pattern matching libraries for design-for-manufacturing (DFM) insertion into the design flow for auto-fixing and physical verification. Patterns are used in a production-ready yield learning methodology to identify and score critical hotspot patterns. Patterns are also used to select sites for process monitoring in the fab.

In this paper, we describe the design of PDB, the methodology for identifying and analyzing patterns across multiple design and technology cycles, and the use of PDB to accelerate manufacturing process learning. One such analysis tracks the life cycle of a pattern from the first time it appears as a potential yield detractor until it is either fixed in the manufacturing process or stops appearing in design due to DFM techniques such as DRC Plus. Another such analysis systematically aggregates the results of a pattern to highlight potential yield detractors for further manufacturing process improvement.

Proceedings Article | 28 March 2014 Paper

A pattern-driven design regularization methodology

Jason Cain, Norma Rodriguez, Jason Sweis, Frank Gennari, Ya-Chieh Lai

Proceedings Volume 9053, 905303 (2014) https://doi.org/10.1117/12.2047741

KEYWORDS: Metals, Manufacturing, Image classification, Logic, Tolerancing, Electroluminescence, Fuzzy logic, Library classification systems, Design for manufacturability, Design for manufacturing

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Proceedings Article | 3 April 2010 Paper

DRCPlus in a router: automatic elimination of lithography hotspots using 2D pattern detection and correction

Jie Yang, Norma Rodriguez, Olivier Omedes, Frank Gennari, Ya-Chieh Lai, Viral Mankad

Proceedings Volume 7641, 76410Q (2010) https://doi.org/10.1117/12.846650

KEYWORDS: Lithography, Manufacturing, Computer simulations, Design for manufacturing, Design for manufacturability, Resolution enhancement technologies, Metals, Standards development, Optical proximity correction, Silicon

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Proceedings Article | 28 May 2004 Paper

Fast algorithm for extraction of worst-case image degradation due to flare

Scott Hafeman, Frank Gennari, Andrew Neureuther

Proceedings Volume 5377, (2004) https://doi.org/10.1117/12.535832

KEYWORDS: Point spread functions, Optical transfer functions, Fourier transforms, Photomasks, Light scattering, Optical proximity correction, Convolution, Feature extraction, Scattering, Manufacturing

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Proceedings Article | 3 May 2004 Paper

Feature level test patterns for characterizing residual process effects

Andrew Neureuther, Gregory McIntyre, Frank Gennari, Michael Lam, Jason Cain, Garth Robins, Edward Huang, Jihong Choi, Ling Wang, Lei Yuan, Hideaki Oshima

Proceedings Volume 5379, (2004) https://doi.org/10.1117/12.540685

KEYWORDS: Plasma etching, Chemical mechanical planarization, Photomasks, Computer aided design, Optical proximity correction, Electronics, Etching, Metrology, Design for manufacturability, Prototyping

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Proceedings Article | 26 June 2003 Paper

Web tool for worst-case assessment of aberration effects in printing a layout

Frank Gennari, Sachan Madahar, Andrew Neureuther

Proceedings Volume 5040, (2003) https://doi.org/10.1117/12.485448

KEYWORDS: Interfaces, Zernike polynomials, Monochromatic aberrations, Raster graphics, Printing, Optical proximity correction, Human-machine interfaces, Java, Binary data, Software development

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Proceedings Article | 27 December 2002 Paper

No-fault assurance: linking fast-process CAD and EDA

Andrew Neureuther, Frank Gennari

Proceedings Volume 4889, (2002) https://doi.org/10.1117/12.467898

KEYWORDS: Photomasks, Computer aided design, Reflectivity, Chemical mechanical planarization, Laser processing, Oxides, Manufacturing, Electronic design automation, Prototyping, Process modeling

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Proceedings Article | 12 July 2002 Paper

Validation of the aberration-pattern-matching OPC strategy

Frank Gennari, Garth Robins, Andrew Neureuther

Proceedings Volume 4692, (2002) https://doi.org/10.1117/12.475679

KEYWORDS: Monochromatic aberrations, Binary data, Optical proximity correction, Spherical lenses, Phase shifts, Computer aided design, Electronic design automation, Fourier transforms, Photomasks, Image processing

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Proceedings Article | 11 March 2002 Paper

Aberrations are a big part of OPC for phase shifting masks

Frank Gennari, Andrew Neureuther

Proceedings Volume 4562, (2002) https://doi.org/10.1117/12.458272

KEYWORDS: Monochromatic aberrations, Binary data, Photomasks, Prototyping, Computer aided design, Optical proximity correction, CAD systems, Printing, C++, Fourier transforms

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Proceedings Article | 14 September 2001 Paper

LAVA web-based remote simulation: enhancements for education and technology innovation

Sang Il Lee, Ka Chun Ng, Takashi Orimoto, Jason Pittenger, Toshi Horie, Konstantinos Adam, Mosong Cheng, Ebo Croffie, Yunfei Deng, Frank Gennari, Thomas Pistor, Garth Robins, Mike Williamson, Bo Wu, Lei Yuan, Andrew Neureuther

Proceedings Volume 4346, (2001) https://doi.org/10.1117/12.435691

KEYWORDS: Printing, Java, Photomasks, Diffusion, Near field, Computer simulations, Optical simulations, Lithography, Human-machine interfaces, Etching

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Showing 5 of 20 publications

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