Mirror-based and zone plate-based imaging systems are being used in actinic extreme ultraviolet (EUV) reticle review tools. With regard to zone plates, a short working distance is advantageous in terms of the required spectral bandwidth, manufacturability, and potential throughput and imaging performance. Zone plates therefore typically have a short working distance. The industry has adopted the use of an EUV pellicle to protect the photomask. Imaging photomask through-pellicle requires a working distance larger than 2.5 mm. A zone-plate-based EUV mask microscope with a 3-mm working distance has been commissioned at beamline 11.3.2 of the Advanced Light Source. Through-pellicle imaging at an exposure time of 2 s is demonstrated. The instrument achieves an image contrast of 95% on large features on a photomask with a tantalum-based absorber. Imaging down to 45-nm half pitch (mask scale) is demonstrated. A NILS of 2.55 is achieved on 60-nm half-pitch (mask scale) lines and spaces. These results demonstrate that zone-plate-based imaging systems can meet the requirements of an actinic EUV mask review tool in terms of imaging performance and throughput in an instrument compatible with EUV pellicles.
With the persistent drive to enable EUV lithography (EUVL) for the continuation of pattern scaling and the close collaborations between suppliers and customers, tremendous progress has been made in the last five years in EUV mask infrastructure development. With the advent of actinic pattern mask inspection (APMI) tool, the only remaining EUV mask infrastructure gap until recently has been closed. We will present real-case examples from inspection of 7nm and 5nm logic node EUV masks with APMI in operation at Intel mask shop and demonstrate that actinic inspection provides defect detection capability beyond the traditional DUV optical and e-beam mask inspection (EBMI) tools for defect control and the guaranty of mask quality. In addition to the main focus on APMI and through-pellicle inspection in this paper, we also provide a brief discussion of other key EUV infrastructure modules for mask production in current EUVL at 0.33NA and future technology extension to enable high NA EUVL at 0.55NA.
This past year has witnessed a sharp increase in EUV lithography progress spanning production tools, source and infrastructure to better position the technology for HVM readiness. While the exposure source remains the largest contributor to downtime and availability, significant strides in demonstrated source power have bolstered confidence in the viability of EUVL for insertion into HVM production. The ongoing development of an EUV pellicle solution alleviates industry concern about one significant source of line-yield risk. In addition to continued expected improvements in EUV source power and availability, the ability to deliver predictable yield remains an ultimate gate to HVM insertion. Ensuring predictable yield requires significant emphasis on reticles. This includes continued pellicle development to enable the readiness and supply of a robust pellicle solution in advance of 250W source power, as well as improvements in mask blank defectivity and techniques to detect and mitigate reticle blank and pattern defects.
The industry is transitioning EUV lithography from feasibility phase to technology development. EUV mask infrastructure
needs to be prepared to support the technology development and ready to enable the implementation of EUV lithography
for production. In this paper, we review the current status and assess the readiness of key infrastructure modules in EUV
mask fabrication, inspection and control, and usage in a mask cycle: blank quality and inspection, pattern inspection, defect
disposition and repair, pellicle integration, and handling of pelliclized masks.
Extreme ultraviolet lithography (EUVL) mask multi-layer (ML) blank surface roughness specification historically comes from blank defect inspection tool requirement. Later, new concerns on ML surface roughness induced wafer pattern line width roughness (LWR) arise. In this paper, we have studied wafer level pattern LWR as a function of EUVL mask surface roughness via High-NA Actinic Reticle Review Tool. We found that the blank surface roughness induced LWR at current blank roughness level is in the order of 0.5nm 3σ for NA=0.42 at the best focus. At defocus of ±40nm, the corresponding LWR will be 0.2nm higher. Further reducing EUVL mask blank surface roughness will increase the blank cost with limited benefit in improving the pattern LWR, provided that the intrinsic resist LWR is in the order of 1nm and above.
Evaluation of lithography process or stepper involves very large quantity of CD measurements and measurement
time. In this paper, we report on an application of Scatterometry based metrology for evaluation of EUV photomask
lithography. Measurements were made on mask level with Ellipsometric scatterometer for develop-check CD (DCCD)
and final check CD (FCCD). Calculation of scatterometer profile information was performed with in-situ library-based
rigorous coupled wave analysis (RCWA) method. We characterized the CD uniformity (CDU) and metal film thickness
uniformity. OCD results show that high precision CD measurement EUV absorber and resist is possible with this
method.
A series of simulations were also performed to investigate the feasibility of Ellipsometric scatterometry for various
pitches/line CD sizes, down to 11nm half-pitch at 1x magnification. The data showed that Scatterometry provides a
nondestructive and faster mean of characterizing mask CD performance for various EUV process generations.
For Extreme Ultra-violet Lithography (EUVL) targeting at 11nm and beyond design rules, the minimum printable
EUVL multilayer (ML) mask defect size can be as small as 20-25nm. As a result, the defect-free EUVL ML mask blank
fabrication remains the top challenge for EUVL mask. Aspects of this challenge include high quality blank substrate
material (low thermal expansion material) fabrication, substrate polishing, substrate cleaning, blank handling, ML
deposition, and high sensitivity substrate and blank defect inspection. High investment cost and potential low blank yield
due to stringent defect-free requirement can quickly drive up EUVL cost of ownership. It is anticipated, however, the
EUVL ML blank yield can be drastically improved if we can allow a few defects on a ML blank. Utilizing such a
"defective" grade mask blank to fabricate a defect-free EUVL mask requires several defect mitigation schemes during
mask patterning processes. These schemes include modifying mask absorber pattern via repair tool to compensate the
effect of an adjacent ML defect and using absorber pattern to cover the ML defects. In this paper, we focused on the
study and demonstration of using device pattern to cover limited number of blank defects. The steps of this defect
mitigation process include blank fiducial mark patterning, defect location relative to fiducial mark precision
measurement, automated pattern shift solution simulation for a given ML defect map, and precision alignment of the
device pattern to the blank defects during e-beam write. With these steps, we have successfully demonstrated the
coverage of several targeted ML blank defects simultaneously via global device pattern shift.
Phase-shifting effect of EUV masks with various absorber thicknesses has been studied both by simulations and
experiments. In EUV lithography, masks with 180 phase shifting absorber work like embedded attenuated phase-shifting
masks. At 66nm thickness of TaN/TaON absorber, 180 degree phase shifting can be achieved in theory. Based on the
experiments, we observed that the true180 degree phase shifting can be achieved with absorber thickness between 66 and
76 nm. In this paper, phase shifting impact of the various thickness absorbers has been characterized. Imaging
performance of masks with 51 nm, 66 nm and 76 nm thick absorber has been experimentally compared. The process
window of various thickness absorber masks are rigorously studied.
Extreme ultraviolet lithography (EUVL)-embedded phase-shift mask (EPSM) for 16-nm half-pitch node technology and beyond generations will provide improvements in process window and low shadowing effect as compared to those of the conventional EUVL binary mask. In a previous study, we experimentally demonstrated the advantages of the EUVL EPSM for the dense lines and contacts as compared to those of the standard EUVL mask. In this study, we focused more on systematic analysis and comparison of the process windows between EUVL EPSM and conventional EUVL binary mask for various feature types. In addition, we investigated the EUVL EPSM performances as a function of phase errors in order to further define the EUVL EPSM absorber thickness uniformity requirements. Both the EUVL EPSM and binary mask were exposed at the Alpha Demo Tool at IMEC, and the wafer level data show features in the EPSM have a larger process window, lower dose-to-target value, and reduced shadowing effect as compared to those of the conventional EUVL binary mask.
When compared to a thick absorber mask, a thin absorber EUV mask is expected to have a comparable process
window, a reduced shadowing effect, and lower MEEF. However, regardless of the mask absorber thickness, the
dark-field in EUV lithography is never 100% dark. Using the same absorber stack composition, EUV masks with
thinner absorbers have inherently higher leakage due to the background transmission propagating through the absorber
stack. While this does act to improve resist sensitivity or throughput, the leakage reduces the image contrast and can
cause CD degradation in "double" exposed regions at the edge of adjacent fields. In this study, EUVL lithographic
benchmarking of both thin and thick absorber masks on the ASML Alpha Demo Tool (ADT) at IMEC is presented.
Herein, we experimentally quantify the process window, EL, LWR, MEEF, Esize, ultimate resolution, and impact of
dark-field background exposures on CDs for both thin and thick absorber masks. There are additional issues when
field edges overlap with adjacent fields, and mitigation strategies for EUV leakage emanating from dark-field regions
are discussed.
Extreme ultra-violet Lithography (EUVL) alternating phase shift mask (APSM) or other optical enhancement
techniques are likely needed for 16nm (half pitch) technology generation and beyond. One possible option is the
combination of EUVL and APSM. The fabrication of EUVL APSM is more difficult than either the fabrication of an
EUVL binary mask or a conventional optical APSM mask. In the case of EUVL APSM, the phase difference in the
two regions (0 and 180-degree phase regions) is created by a phase step in the substrate prior to the multilayer (ML)
coating. The step height that induces 180-degree phase mismatch in the ML is determined by [λ/(4cosθ)](2m+1),
where m are integers (0, 1, 2,...). In this experiment, we targeted for a step height with m=1. The same mask design
also contains the standard binary structures so that the comparison between the EUVL APSM and the EUVL binary
mask can be performed under the same illumination and wafer process conditions. The EUVL APSM mask was
exposed using Nikon's EUV1 scanner in Kumagaya Japan. The wafer level results showed higher dense line
resolution for EUVL APSM as compared to that of EUVL binary mask. APSM also showed improved line width
roughness (LWR) and depth of focus (DoF) as compared to the best EUVL binary results obtained with C-dipole
off-axis illumination (OAI). The wafer CD resolution improvement obtained by APSM in this experiment is
partially limited by the resist resolution and the mask phase edge spread during ML deposition. We believe that
wafer CD resolution and can further be improved with imaging imbalance compensation mask design and
improvements in resist resolution and the phase generation portion of the mask fabrication process. In this paper, we
will discuss in detail the mask fabrication process, wafer level data analysis, and our understanding of EUVL APSM
related issues.
Extreme ultraviolet lithography (EUVL) is a leading technology to succeed optical lithography for high volume
production of 22 nm node and beyond. One of the top risks for EUVL is the readiness of defect-free masks, especially
the availability of Mo/Si mask blanks with acceptable defect level. Fast, accurate and repeatable defect inspection of
substrate and multi-layer (ML) blank is critical for process development by both blank suppliers and mask makers. In
this paper we report the results of performance improvements on a latest generation mask blank inspection tool from
Lasertec Corporation; the MAGICS M7360 at Intel Corporation's EUV Mask Pilot Line. Inspection repeatability and
sensitivity for both quartz substrates (Qz) and ML blanks are measured and compared with the previous Phase I tool
M7360. Preliminary results of high speed scan correction mirror implementation are also presented
EUV lithography is considered one of the options for high volume manufacturing (HVM) of 16 nm MPU node devices
[1]. The benefits of high k1(~0.5) imaging enable EUVL to simplify the patterning process and ease design rule
restrictions. However, EUVL with its unique imaging process - reflective optics and masks, vacuum operation, and
lack of pellicle, has several challenges to overcome before being qualified for production. Thus, it is important to
demonstrate the capability to integrate EUVL into existing process flows and characterize issues which could hamper
yield. A patterning demonstration of Intel's 32 nm test chips using the ADT at IMEC [7] is presented, This test chip
was manufactured using processes initially developed with the Intel MET [2-4] as well as masks made by Intel's mask
shop [5,6]. The 32 nm node test chips which had a pitch of 112.5 nm at the trench layer, were patterned on the ADT
which resulted in a large k1 factor of 1 and consequently, the trench process window was iso-focal with MEEF = 1. It
was found that all mask defects detected by a mask pattern inspection tool printed on the wafer and that 90% of these
originated from the substrate. We concluded that improvements are needed in mask defects, photospeed of the resist,
overlay, and tool throughput of the tool to get better results to enable us to ultimately examine yield.
EUV blank non-flatness results in both out of plane distortion (OPD) and in-plane distortion (IPD) [3-5]. Even for extremely flat masks (~50 nm peak to valley (PV)), the overlay error is estimated to be greater than the allocation in the overlay budget. In addition, due to multilayer and other thin film induced stresses, EUV masks have severe bow (~1 um PV). Since there is no electrostatic chuck to flatten the mask during the e-beam write step, EUV masks are written in a bent state that can result in ~15 nm of overlay error. In this article we present the use of physically-based models of mask bending and non-flatness induced overlay errors, to compensate for pattern placement of EUV masks during the e-beam write step in a process we refer to as E-beam Writer based Overlay error Correction (EWOC). This work could result in less restrictive tolerances for the mask blank non-flatness specs which in turn would result in less blank defects.
Extreme Ultraviolet Lithography (EUVL) masks have residual stress induced by several thin films on low thermal
expansion material (LTEM) substrates. The stressed thin films finally result in convex out-of-plane displacement (OPD)
of several 100s of nm on the pattern side of the mask. Since EUVL masks are chucked on EUVL scanners differently
from on e-beam writer, the mask pattern placement errors (PPE) are necessary to be corrected for to reduce overlay
errors. In this paper, experimental results of pattern placement error correction using standard chrome on glass (COG)
plate will be discussed together with simulations. Excellent agreement with simple bending theory is obtained.
Suitability of the model to compensate for other EUVL-related PPEs due to mask non-flatness will be discussed.
Extreme ultraviolet lithography (EUVL) tool development achieved a big milestone last year as two full-field
Alpha Demo Tools (ADT) were shipped to customers by ASML. In the future horizon, a full field "EUV1" exposure
tool from Nikon will be available by the end of 20071 and the pre-production EUV exposure tools from ASML are
targeted for 20092. It is essential that high quality EUVL masks can be made and delivered to the EUVL tool users to
support the technology development. In the past year, we have demonstrated mask fabrication with low stress absorber
deposition and good etch process control yielding a vertical etch profile and a mask CD control of 5.7 nm for 32 nm (1x)
space and 7.4 nm for 32 nm (1x) lines. Mask pattern resolution of 15 nm (1x) dense lines was achieved. Full field
reflective mask die-to-die inspection at a 125nm pixel size was demonstrated after low defect multilayer blanks became
available.
In this paper, we will present details of the Intel EUVL Mask Pilot Line progress in EUVL mask defect reduction,
pattern CD performance, program defect mask design and inspection, in-house absorber film development and its
performance, and EUVL metrology tool development. We will demonstrate an overall improvement in EUV mask
manufacturing readiness due to our Pilot Line activities.
Mask defect specifications not only are needed to ensure quality masks for acceptable resist patterning on wafers, but also are utilized as a common goal for tool development, noticeably for mask inspection and repair. Defect specifications are generally determined by the allowable critical dimension (CD) changes from 'defect printability' experiments where a programmed defect mask (PDM) with intentionally placed defects is exposed in a stepper and the changes in resist CDs are measured. With the recent availability of extreme ultra-violet micro-exposure tools (EUV MET), a small field stepper with a numerical aperture (NA) of 0.3, 5X reduction and adjustable degrees of coherence, we are able for the first time to perform extensive studies of pattern defect printability for EUV masks with a high NA exposure tool. Such studies have investigated the defect impact to feature CDs for three different types of patterns: poly gate layer, contacts, and dense lines and spaces. This paper presents the experimental results and analysis of printability data collected under two illumination conditions, annular and dipole, on the MET with full focus and dose matrix (FEM). We have investigated as many as 10 types of defects designed on the PDM for each pattern layer. For each type of defect, a total of 15 sizes are coded on the PDM. With the consideration of limited resolution and line edge roughness of current EUV resists commonly used for EUV lithography development, the CDs under study were chosen in the range of about 40nm to 70nm. Extrapolations from these data are made to predict pattern defect specifications for smaller resist line features. Resist resolution is the main reason for the discrepancies between aerial image simulations and data presented in this paper.
Extreme ultraviolet lithography (EUVL) is one of the leading candidates for the next generation lithography. As the requirement on critical dimension (CD) and side wall profile control becomes ever stringent as minimum feature sizes keep shrinking following the Semiconductor Industry Association (SIA) roadmap, the patterning of the EUV mask absorber material, cost of ownership (COO) of mask, and the capability for defect free EUV masks become the crucial path in enabling the overall success of EUV lithography. The purpose of this study is to understand the etch characteristics in TaN-based EUV mask absorber etch, which will enable us to determine robust process condition in terms of CD performance and profile control. In this paper, CD bias performance in TaN-based EUV mask absorber etching is investigated within inductively coupled plasma (ICP) of fluorine-containing and chlorine-containing gas chemistries. The effects of etch parameters, such as plasma source power, bias power, and pressure, on the CD bias are evaluated through design of experiments (DOE). Some other etching characteristics like etch rate and selectivity are also correlated to the CD performance and etch profile to understand the basic etch mechanism in TaN etch. Latest etch results of the TaN-based absorber are also presented.
It becomes increasingly important to have an integrated process for Extreme UltraViolet (EUV) mask fabrication in order to meet all the requirements for the 32 nm technology node and beyond. Intel Corporation established the EUV mask pilot line by introducing EUV-specific tool sets while capitalizing on the existing photomask technology and utilizing the standard photomask equipment and processes in 2004. Since then, significant progress has been made in
many areas including absorber film deposition, mask patterning optimization, mask blank and patterned mask defect inspection, pattern defect repair, and EUV mask reflectivity metrology. In this paper we will present the EUV mask process with the integrated solution and the results of the mask patterning process, Ta-based in-house absorber film deposition, absorber dry etch optimization, EUV mask pattern defect inspection, absorber defect repair, and mask reflectivity performance. The EUV resist wafer print using the test masks that are fabricated in the EUV mask pilot line will be discussed as well.
To reduce the risk of EUV lithography adaptation for the 32nm technology node in 2009, Intel has operated a EUV mask Pilot Line since early 2004. The Pilot Line integrates all the necessary process modules including common tool sets shared with current photomask production as well as EUV specific tools. This integrated endeavor ensures a comprehensive understanding of any issues, and development of solutions for the eventual fabrication of defect-free EUV masks. Two enabling modules for "defect-free" masks are pattern inspection and repair, which have been integrated into the Pilot Line. This is the first time we are able to look at real defects originated from multilayer blanks and patterning process on finished masks over entire mask area.
In this paper, we describe our efforts in the qualification of DUV pattern inspection and electron beam mask repair tools for Pilot Line operation, including inspection tool sensitivity, defect classification and characterization, and defect repair. We will discuss the origins of each of the five classes of defects as seen by DUV pattern inspection tool on finished masks, and present solutions of eliminating and mitigating them.
The Intel lithography roadmap calls for Extreme Ultraviolet Lithography (EUVL) to be used for the 32 nm node. With the installation of the EUV Micro-Exposure Tool (MET) complete, Intel now has the world's first integrated EUVL process line including the first commercial EUV exposure tool. This process line will be used to develop the EUV technology, including mask and resist, and to investigate issues such as defect printability. It also provides a test-bed to discover and resolve problems associated with using this novel technology in a fab (not lab) environment. Over 22,000 fields have been exposed, the discharge-produced plasma light source has operated for 50,000,000 pulses, 8 masks have been fabricated, and 8 resists have been characterized. The MET combines high resolution capability with Intel's advanced processing facilities to prepare EUVL for high-volume manufacturing (HVM).
In this paper we review the MET installation and facilities, novel capabilities of the linked track, data on optics quality and modeled tool capability, and the MET mask fabrication process. We present data on tool performance including printing 45 nm 1/2 pitch lines with 160 nm depth of focus and 27 nm isolated lines. We show tool accuracy and repeatability data, and discuss issues uncovered during installation and use.
The introduction of extreme ultraviolet (EUV) lithography into high volume manufacturing requires the development of a new mask technology. In support of this, Intel Corporation has established a pilot line devoted to encountering and eliminating barriers to manufacturability of EUV masks. It concentrates on EUV-specific process modules and makes use of the captive standard photomask fabrication capability of Intel Corporation. The goal of the pilot line is to accelerate EUV mask development to intersect the 32nm technology node. This requires EUV mask technology to be comparable to standard photomask technology by the beginning of the silicon wafer process development phase for that technology node. The pilot line embodies Intel's strategy to lead EUV mask development in the areas of the mask patterning process, mask fabrication tools, the starting material (blanks) and the understanding of process interdependencies. The patterning process includes all steps from blank defect inspection through final pattern inspection and repair. We have specified and ordered the EUV-specific tools and most will be installed in 2004. We have worked with International Sematech and others to provide for the next generation of EUV-specific mask tools. Our process of record is run repeatedly to ensure its robustness. This primes the supply chain and collects information needed for blank improvement.
Extreme Ultraviolet Lithography (EUVL) reflective mask blank development includes low thermal expansion material fabrication, mask substrate finishing, reflective multi-layer (ML) and capping layer deposition, buffer (optional)/absorber stack deposition, EUV specific metrology, and ML defect inspection. In the past, we have obtained blanks deposited with various layer stacks from several vendors. Some of them are not commercial suppliers. As a result, the blank and patterned mask qualities are difficult to maintain and improve. In this paper we will present the evaluation results of the EUVL mask pattering processes with the complete EUVL mask blanks supplied by the commercial blank supplier. The EUVL mask blanks used in this study consist of either quartz or ULE substrates which is a type of low thermal expansion material (LTEM), 40 pairs of molybdenum/silicon (Mo/Si) ML layer, thin ruthenium (Ru) capping layer, tantalum boron nitride (TaBN) absorber, and chrome (Cr) backside coating. No buffer layer is used. Our study includes the EUVL mask blank characterization, patterned EUVL mask characterization, and the final patterned EUVL mask flatness evaluation.
Using ruthenium (Ru) material as an extreme ultraviolet lithography (EUVL) mask blank multi-layer (ML) capping presents many advantages over silicon (Si) capping layer. Its high resistance to oxidation has been tested in EUVL optics. Ru capped ML mask blank also demonstrated very high etch selectivity during both mask absorber etch when the blank has no buffer layer and during buffer etch when the blank contains buffer layer. Due to higher EUV light absorption, Ru capping layer usually has to be much thinner than that of Si capping layer. As a result, long-term mask lifetime with thin Ru capping layer and its stability during multiple mask cleans becomes a concern. To address these concerns, we developed a process that improves Ru capped ML reflectivity for a given capping thickness. We further demonstrated the shelf lifetime stability of Ru capped ML mask blank and stability during multiple mask cleans. In this paper, we will discuss the detailed performance of Ru capped ML blanks, which includes mask blank reflectivity performance for different capping thickness, Ru capped ML mask blank shelf lifetime stability and cleaning stability performance. Mask patterning results using Ru capped ML blanks will also be presented.
The source of flare in EUVL systems is mostly from the mid-spatial frequency roughness (1 /μm - 1 /mm spatial periods) of mirrors. Due to the challenges in polishing mirrors to a small fraction of the wavelength, flare in EUV lithography tools is expected to be greater than flare in current DUV tools. Even though EUV flare is constant across the field, there can be within-die flare variations due to variations in layout density. Hence, it is expected that to meet the CD control requirements for the 32 nm node, Flare Variation Compensation (FVC), akin to Optical Proximity Correction (OPC) would be required. FVC needs the within-die flare level estimated by convolving the Point Spread Function due to scatter (PSFsc) with the mask layout. Thus, accurate knowledge of the system PSFsc is essential for FVC. Experimental results of the Modulation Transfer Function (MTF) technique to estimate flare and the PSFsc of the Engineering Test Stand (ETS) are presented. It was also determined that due to the nature of the PSFsc in EUVL tools a more accurate measure for flare would be to use the 0.5 μm line as opposed to the current 2 μm line standard for measuring flare on DUVL tools.
Silicon (Si) capping for extreme ultra-violet lithography (EUVL) multilayer (ML) mask blank presents certain disadvantages, such as prone to oxidation, low chemical resistance, low SiO2 buffer layer etch selectivity to the capping layer. These performance and process issues with Si capped ML mask blank will reduce mask lifetime and require tighter process margin during EUVL mask processing. Using ruthenium (Ru) to replace Si for ML capping has been investigated previously for EUVL optics application. High oxidation resistance for Ru capped ML optics has been demonstrated. In this study, we have further demonstrated that Ru capped ML mask blank can also overcome the process issues that are associated with the Si capping. Our mask patterning results showed very high absorber and buffer etch selectivity to the Ru capping layer. As a result, uniform mask reflectivity after mask patterning is obtained.
In this paper we will present detailed Ru capped ML mask fabrication results, such as etch profile, etch selectivity to the ML capping, as well as mask quality characterization results, which include ML performance data comparison before and after the mask patterning.
Early production EUV exposure tools may have difficulty achieving flare requirements in the 5-6% range for the 32nm technology node. In this case, flare compensation may be needed to achieve the necessary CD control budget for production. This paper explores both experimentally as well as computationally wafer CD compensation though mask CD resizing so that proper CD control across the exposure field can be maintained. Experimental resist data collected on POB#2 of the Engineering Test Stand (ETS) suggest that even a simple linear CD compensation model can signifantly improve CD contorl in the presence of flare variation. Extending a similar concpet to a hypothetical full-field 25×33 mm2 mask area containgin 20 nm gate CDs shwos taht CD compensation, while computationally demanding, can be realized through a convolution approach of a 1×1 mm2 mask area using a non-uniform adaptive grid.
While interferometry is routinely used for the characterization and alignment of lithographic optics, the ultimate measure of performance for these optical systems is the transfer of an image or pattern into photoresist. Simple yet flexible exposure systems play an important role in this task because they allow complex system-dependent effects to be isolated from the printing results. This enables the most direct lithography evalaution of the optical system under investigation. To address tehse issues for commercial-class EUV optics, a synchrotron-based programmable illuminator exposrue station has been implemented at Lawrence Berkeley National Laboratory (the Advanced Light Source). As previously presented, this static microfield exposure system has been used to lithography characterize a 4-mirror optical system designed for the EUV Engineering Test Stand (ETS) prototype stepper. Based on the lithographic characterization, here we present a detailed performance analysis of the 0.1-NA ETS Set-2 optic. Operation of the static printing system with the Set-2 optic yielded approximately 330 exposed wafers, where each wafer contains one or more focus-exposure matrices. A wide variety of parameters were studied includign, among others, illumination conditions, resist thickness, and mask tone. Here we present a subset of this data in terms of process-window results. The resutls demonstrate a depth of focus (DOF) approximately 2μm for isolated 70-nm line features, 1 μm for nested 70-nm line features, and 0.5μm for 70-nm contacts on 270-nm pitch.
Extreme Ultraviolet Lithography (EUVL) is the leading candidate for the 45 nm node technology and beyond. A mask film structure and material selection become increasingly important for a success in the EUVL mask process development. Etch CD performance is considered in the material selection of an EUV mask absorber stack.
This paper reports the study of etch CD performance and pattern loading effects in the plasma etch on two potential absorber materials of Cr and TaN. The etch process was experimentally setup on wafer samples and two different film etches were conducted in the same etch chamber. The CD data was collected on an SEM and was used for the CD performance analysis and comparison.
In this study, it was found that the process etch CD bias in the TaN etch was significantly smaller than that in the Cr etch due to a fast etch rate of the TaN etch. The variation of the etch CD bias in the TaN etch was slightly higher than that in the Cr etch. The global pattern density changes had less impact to the Cr etch bias than the TaN etch bias.
Static and scanned images of 100 nm dense features were successfully obtained with a developmental set of projection optics and a 500W drive laser laser-produced-plasma (LPP) source in the Engineering Test Stand (ETS). The ETS, configured with POB1, has been used to understand system performance and acquire lithographic learning which will be used in the development of EUV high volume manufacturing tools. The printed static images for dense features below 100 nm with the improved LPP source are comparable to those obtained with the low power LPP source, while the exposure time was decreased by more than 30x. Image quality comparisons between the static and scanned images with the improved LPP source are also presented. Lithographic evaluation of the ETS includes flare and contrast measurements. By using a resist clearing method, the flare and aerial image contrast of POB1 have been measured, and the results have been compared to analytical calculations and computer simulations.
While interferometry is routinely used for the characterization and alignment of lithographic optics, the ultimate performance metric for these optics is printing in photoresist. The comparison of lithographic imaging with that predicted from wavefront performance is also useful for verifying and improving the predictive power of wavefront metrology. To address these issues, static, small-field printing capabilities have been added to the EUV phase- shifting point diffraction interferometry implemented at the Advanced Light Source at Lawrence Berkeley National Laboratory. The combined system remains extremely flexible in that switching between interferometry and imaging modes can be accomplished in approximately two weeks.
For optical inspection of Extreme Ultraviolet Lithography (EUVL) masks using Deep Ultraviolet (DUV) light, contrast from reflected light is used to form the image of the mask and detect the defects. The inspectability of a patterned mask depends on the optical properties, surface conditions and thickness of absorber and buffer layer. The issue in EUVL mask inspection is the relatively low image contrast in the inspection tool because both the EUV-reflective and EUV-absorbing regions reflect DUV light. The need of a buffer layer to protect the multilayer (ML) reflector during mask processing and defect repair necessitates two inspections for a patterned mask: one with the buffer layer on to find the defect for repair and one with the buffer layer removed to qualify a final mask. Since the ML appears bright at DUV inspection wavelengths, the buffer layer is also chosen to give high reflectivity. Therefore, the absorber reflectivity must be low enough to provide high image contrast and to avoid the edge interference effect. Recently, we have developed a surface treatment process to reduce the reflectivity of absorber layer and result in a DUV contrast approaching 90 percent. This greatly improves the optical inspectability of EUVL mask to a level similar to conventional transmission mask. In this paper, we describe the overall EUVL mask inspection strategy and present a comprehensive discussion on mask optimization in materials selection and modification for high inspectability. We report the reflectivity of Mo-Si multilayer, buffer layers using SiO2 and Ru, and absorber layers of Cr and TaN. We will demonstrate with DUV inspection images of the optimized EUVL masks that the image contrast and quality from reflected light are close to those of conventional photo-masks with transmitted light. This greatly enhanced EUVL mask inspectability will increase defect detectability for inspection tools and simplify image rendering in die-to-database inspection.
The EUV mask patterning process development depends on the choice of EUV mask absorber material, which has direct impact on the mask quality or performance such as CD control, defect control, and registration. In the past, several EUV mask absorber material candidates that include Al-Cu, Ti, TiN, Ta, TaN, and Cr have been evaluated. Our research indicated that TaN and Cr are the better candidates among the others evaluated. Cr absorber has been used for many optical lithography generations. Further extending Cr mask absorber to EUV lithography presents minimum impact to the currently mask technology infrastructure. TaN is a new film that has not been used in the currently mask technology. However, Ta based metal compound has been studied previously in x-ray mask technology. Its performance in EUV mask fabrication and printing was found compatible and comparable in many process steps and performance aspects to that of Cr absorber. In this paper, we will present our research and development work on TaN absorber EUV mask fabrication and characterization. The studies include material deposition study, etch development, cleaning compatibility evaluation, and mask printing test. The TaN absorber etch was able to achieve good etch profile and high etch selectivity to the buffer oxide layer. The cleaning benchmarking results showed that TaN absorber is compatible to the currently acid based Cr cleaning procedures and solution. No material damage or loss was found in the case of extreme harsh cleaning conditions used. The TaN thin absorber mask was successfully fabricated and printed in 10x microstepper at Sandia National Lab. Minimum feature of 70nm L/S were obtained.
A Cr film is one of the attractive materials that have been evaluated as an absorber in the advanced mask development for the extreme ultraviolet lithography (EUVL). The EUV absorber material needs to meet the requirement in EUV absorbance, mask process, inspection, repair and others. Two EUV masks were fabricated in a research laboratory and tested on a lOx reduction EUV exposure system. The processes of fabricating these two masks started with an 8-inch silicon wafer blank that had the Mo/Si multilayer (ML). A Cr film was selected as an absorber for both masks. A Si02 film, served as a buffer layer, was applied to one of the masks. The mask patterning was carried on a conventional I-line exposure tool following plasma dry etch for pattern transfer. The functionality of the two masks was tested in a resist image printing. This paper reports the EUV mask fabrication process and discusses the two different approaches to fabricate an EUV mask. 80 nm resist image features were resolved on a lOx reduction EUV exposure system by using these two masks.
Minimizing image placement errors due to thermal distortion of the mask is a key requirement for qualifying EUV Lithography as a Next Generation Lithography (NGL). Employing Low Thermal Expansion Materials (LTEMs) for mask substrates is a viable solution for controlling mask thermal distortion and is being investigated by a wide array of researchers, tool makers, photomask suppliers, and material manufacturers. Finite element modeling has shown that an EUVL mask with a Coefficient of Thermal Expansion (CTE) of less than 20 ppb/K will meet overlay error budgets for <EQ 70 nm lithography at a throughput of 80 wafers per hour. In this paper, we describe the functional differences between today's photomask and EUVL masks; some of these differences are EUVL specific, while others are natural consequences of the shrinking critical dimension. We demonstrate that a feasible manufacturing pathway exists for Low Thermal Expansion Material (LTEM) EUVL masks by fabricating a wafer-shaped LTEM mask substrate using the same manufacturing steps as for fabricating Si wafers. The LTEM substrate was then coated with Mo/Si multilayers, patterned, and printed using the 10X Microstepper. The images were essentially indistinguishable from those images acquired from masks fabricated from high quality silicon wafers as substrates. Our observations lend further evidence that an LTEM can be used as the EUVL mask substrate material.
In this paper, we will present our research work in EUVL mask absorber characterization and selection. The EUV mask patterning process development depends on the choice of EUVL mask absorber material, which has direct impact on the mask quality such as critical dimension (CD) control, and registration. EUVL mask absorber material selection consideration involves many aspects of material properties and processes. These include film absorption at EUV wavelength, film emissivity, film stress, mask CD and defect control, defect inspection contrast, absorber repair selectivity to the buffer layer, etc. The selection of the best candidate is non-trivial since no material is found to be superior in all aspects. In an effort of searching the best absorber materials and processes, we evaluated Al-Cu, Ti, TiN, Ta, TaN, and Cr absorbers. The comparison of material intrinsic properties and process properties allowed us to focus on the most promising absorbers and to further develop the corresponding processes to meet EUVL requirement.
In this paper, the effects of mask line edge roughness (LER) transfer in both deep ultra-violet (DUV) and extreme ultra- violet (EUV) lithography patterning is studied experimentally. In order to understand how the mask LER transfers in the wafer printing process under both DUV and EUV lithography, an optical mask with programmed LER was fabricated. The EUV mask was further fabricated by using the optical mask via optical lithography pattern transfer. The programmed LER on both optical mask, EUV mask, and printed resist images were characterized, measured, and compared. The data analysis showed that the mask LER in both DUV and EUV cases transferred to wafer with a scaling factor much less than one regardless of lithographic k1-factors. The LER transfer does not resemble the case of mask CD error transfer, in which scale factors greater than one for small lithographic k1-factor occur. The primary reason for the difference is that the amount of mask LER transferred to the wafer strongly depends on the total area of the LER, i.e. depends on both vertical and horizontal dimension of the LER. This case is very similar to that of a single mask defect transfer.
We report on the comparison of defect printability experimental results with at-wavelength defect inspection and printability modeling at extreme ultraviolet (EUV) wavelengths. Two sets of EUV masks were fabricated with nm- scale substrate defect topographies patterned using a sacrificial layer and dry-etch process, while the absorber pattern was defined using a subtractive metal process. One set of masks employed a silicon dioxide film to produce the programmed defects, whereas the other set used chromium films. Line-, proximity- and point-defects were patterned and had lateral dimensions in the range of 0.2 micrometer X 0.2 micrometer to 8.0 micrometer X 1.5 micrometer on the EUV reticle, and a topography in the range of 8 nm - 45 nm. Substrate defect topographies were measured by atomic force microscopy (AFM) before and after deposition of EUV-reflective Mo/Si multilayers. The programmed defect masks were then characterized using an actinic inspection tool. All EUVL printing experiments were performed using Sandia's 10x- reduction EUV Microstepper, which has a projection optics system with a wavefront error less than 1 nm, and a numerical aperture of 0.088. Defect dimensions and exposure conditions were entered into a defect printability model. In this investigation, we compare the simulation predictions with experimental results.
In the last two years, we have developed tow Extreme UV (EUV) mask fabrication process flows, namely the substractive metal and the damascene process flows, utilizing silicon wafer process tools. Both types of EUV mask have been tested in a 10X reduction EUV exposure system. Dense lines less than 100 nm in width have been printed using both 0.6 micrometers thick top surface imaging resists and ultra-thin DUV resist. The EUV masks used in EUV lithography development work have been routinely made by using the current wafer process tools. The two EUV mask processes that we have developed both have some advantages and disadvantages. The simpler subtractive metal process is compatible with the current reticle defect repair methodologies. On the other hand, the more complex damascene process facilitates mask cleaning and particle inspection.
In this paper, the Extreme Ultra Violet (EUV) mask absorber repair using focused ion beam (FIB) is investigated. It is well known that focused ion beam repair for the opaque defect removal can easily cause both damage and gallium staining or contamination to the substrate. The damage and gallium staining will induce a localized transmission loss in the case of conventional transmission optical mask. The situation become even worse in the case of reflective EUV mask since gallium is very absorbent at EUV wavelength of 13.4 nm. In addition, the incident beam travels double path through the damaged region due to the reflective nature of the mask. To minimize or even eliminate the repair induced damage, we designed a mask flow to incorporate a SiO2 sacrificial layer beneath the metal absorber layer. This sacrificial layer will become a buffer layer for the metal defect repair. The repair, therefore, will only result in the damage on the sacrificial SiO2 layer instead of EUV reflective multilayer (ML). After the repair, the damaged and contaminated SiO2 layer will be etched away by either wet or dry etch. In the study, we performed both high voltage of 30 kv repair and low voltage of 10 kv repair. We found that in addition to use a sacrifice layer, low voltage focused ion beam repair is also necessary to ensure the damage and contamination free ML substrate.
The maturity and acceptance of top surface imaging (TSI) technology has been hampered by several factors including inadequate resist sensitivity and silylation contrast, defects and line edge roughness and equipment performance/reliability issues. We found that the use of a chemically amplified resist can improve the sensitivity by a factor of 1.5 - 2X, without compromising line edge roughness. While the post-silylation contrast of this chemically amplified material is poor ((gamma) < 1), the post-etch contrast is excellent ((gamma) >> 10) and the use of advanced silylation chemistries (disilanes) can further reduce the dose-to-size and increase the contrast. We have also demonstrated that using sulfur dioxide in the plasma etch process can improve the sidewall passivation of the resist lines, thus reducing the overall line edge roughness. Finally, we have been able to successfully use the TSI process to pattern deep sub-micron polysilicon and metal patterns.
In this paper, the printability of Extreme UV (EUV) mask defects at 100 nm design rule is studied via top surface imaging (TSI) resist process. The EUV mask defect size requirement is determined by taking into account the wafer process critical dimension (CD) variability. In the experiment, a programmed EUV absorber defect mask was first fabricated by subtractive metal patterning on a Mo/Si multilayer-coated silicon wafer substrate. The 10X experimental EUV lithography system with 13.4 nm exposure wavelength and 0.08 NA imaging lens was used to expose the programmed defect mask. The resists CD response to the metal absorber mask defect area is measured under different process conditions, i.e., different exposure doses. It is found that similar to a single-layer DUV resist cases that have been studied before, the EUV resist CD responds to the mask defect area linearly for small mask defects. From such a set of CD-defect response lines, the allowable absorber mask defect requirement is assessed via the statistical explanation of the printable mask defect size, which is tied to the wafer process specifications and the actual wafer process CD controllability. Our results showed that a clear and an opaque intrusion absorber mask defect as small as 60- 80 nm is printable at 100 nm design rules. Based on the statistical defect printability analysis method that we have developed, the printable mask defect size can always be redefined without additional data collection when the process controllability or the process specification changes.
The goal of this investigation was to develop a 0.3 micron silylation process for 248 nm exposure, using a commercial photoresist material. Presented are results from investigation into liquid silylation of 248 nm exposure of Dynachem EL IRTM, a non-melamine image reversal novalac material designed for i-line application. A GCA BOLD 0.42 NA, 248 nm excimer laser projection system was used for exposure. A process has been developed utilizing a silylation solution of hexamethyl- cyclotrisilazane (HMCTS), propylene-glycol-methyl-ether-acetate (PGMEA), and xylene mixtures. Using a 15 run Box-Behnken statistically designed experiment, dry development in 02 RIE has been optimized with chamber pressure, flow rate, and 02 flow as process factors. Process responses optimized were selectivity, etch rate, and anisotropy. Results show capabilities and sensitivities of the process. Response surfaces are presented, along with resist image results of 0.3 microns at 5:1 aspect ratio.
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