Process Window Qualification (PWQ) is a well-known wafer inspection technique used to qualify the IC manufacturing lithography process window. Circuit designs are becoming denser and more complex in advanced semiconductor process technologies. Therefore, yield is becoming increasingly sensitive to defects. How to detect wafer defects at an early stage is the key to improving wafer yield. Additionally, shortening the PWQ total turn around run time is an important factor for a wafer yield improvement methodology. In this paper, the Winbond OPC team and Cadence Pegasus DFM team initiated a project to improve the PWQ run time and accuracy using a pattern analysis flow. This flow includes defect data pre-processing, classification, and filtering, including the use of CD-SEM image auto-alignment to improve extraction locations and wafer results. The huge data volumes are reduced in order to create easy to review results. This flow reduces the PWQ processing time and correctly finds real wafer defects to improve process windows and yield.
For advanced technology nodes, it’s critical to utilize resolution enhancement technique (RET) methods to improve pattern fidelity and wafer yield. Conventional techniques including rule-based SRAF (RB-SRAF) and model-based SRAF (MBSRAF) methods have been widely adopted to increase the manufacturing process window. ILT delivers superior imaging performance compared to both RB-SRAF and MB-SRAF methods, at the expense of slower performance and more inconsistency issue. Recent advancement of machine learning techniques opens up new gateways for more RET enhancements by overcoming these challenges, thus providing a pathway to extend ILT solution to full chip design. In this paper, we developed an end-to-end flow that seamlessly incorporated model training and application for full chip ILT MBSRAF generation and optimization via POLY-GAN, a new Generative Adversarial network (GAN) geared for fast, in-context and accurate ILT MB-SRAF synthesis. An image based deep learning architecture similar to pix2pix conditional GAN was utilized in our study. In this paper, we demonstrate that ML based full chip ILT MBSRAF generation yields superior process window compared to rule based SRAF generation, while maintaining comparable run-time performance.
Optical Proximity Correction (OPC) is an important step in the optical lithography-based manufacturing process. Starting from 115 nm, lithography processes typically use OPC to resolve features acceptably. Advanced OPC technologies use model-based edge segment adjustments to achieve highly accurate corrections. The typical process for optical proximity correction suffers from a huge turn-around-time (TAT) and is well known to have time-consuming complexity especially at 40 nm and below. Therefore, in order to speed up process development and increase qualified pattern variations with good yield, we must find ways to speed up the OPC TAT. This paper presents a flow to construct layout hierarchy and increase OPC cell/template re-use to greatly reduce the OPC TAT using the Pegasus Computational Pattern Analytics (CPA) software.
Circuit designs are becoming denser and more complex in advanced semiconductor process technologies. The foundry process windows are becoming smaller and smaller which increases sensitivity to wafer surface defects. These defects should be detected early to resolve the root causes and eventually help to improve the yield. Wafer defects are still often inspected manually while the defect counts can reach into the millions. It takes a long time to analyze and review the results while the identification of the root causes may be less accurate and buried in noise. In this paper, UMC advance research teams, in collaboration with the Cadence DFM team, utilized the Pegasus Computational Pattern Analytics (CPA) software to develop an enhanced inspection flow. This flow includes defect data preprocessing, classification, filtering, and reduction of huge data volumes to create visible and easy to review results. By finding more accurate root causes, we could reduce process develop time and finally improve wafer yields.
Beyond the 40nm technology node, layout weak points and hotspot types increase dramatically. Many hotspots can be detected by OPC simulation. However, in advanced nodes, OPC simulation suffers from a long turn-around-time (TAT) and is challenged to handle the additional design complexity. Therefore, in order to speed up the process and OPC development, an efficient OPC hotspot detection method is required. This paper presents a flow using Pegasus Computational Pattern Analytics (CPA) technology from Cadence to extract a comprehensive set of patterns to build a pattern bank from a layout source. We can then compare two or more different banks (diffing) to find new patterns which have not been processed before. OPC engineers can analyze these new patterns to check for any OPC issues instead of simulating a full chip. This flow provides a much higher efficiency and better performance while allowing the storage of pattern banks over time to build history and yield experience. Over time, each new layout introduced for OPC can be processed faster because more patterns have been added to the banks and less simulation time is needed.
KEYWORDS: Chemical mechanical planarization, Copper, Metals, Systems modeling, Data modeling, Oxides, Calibration, Performance modeling, Back end of line, Process modeling
As we move to more advanced nodes, the number of Chemical Mechanical Polishing (CMP) steps in semiconductor processing is increasing rapidly. CMP is known to suffer from pattern dependent variation such as dishing, erosion, recess, etc., all of which can cause performance and yield issues. One such yield issue seen in back end of line (BEOL) Cu interconnect CMP processes is pooling. Pooling exists when there is uncleared bulk Cu and/or barrier residue remaining after final CMP step, leading to shorts between neighboring interconnect lines. To detect potential pooling locations on a given design, for a given CMP process, predictive CMP models are needed. Such models can also aid in CMP process and chip design optimizations. In this paper we discuss how a pattern dependent CMP effect that we call the “local neighborhood effect” causes large recesses that can lead to pooling in Cu interconnect CMP processes. We also discuss modeling this effect as part of an advanced predictive CMP modeling system and show how the resulting modeling system accurately predicts Cu pooling on several 14 nm designs.
Along with process improvement and integrated circuit (IC) design complexity increased, failure rate caused by optical getting higher in the semiconductor manufacture. In order to enhance chip quality, optical proximity correction (OPC) plays an indispensable rule in the manufacture industry. However, OPC, includes model creation, correction, simulation and verification, is a bottleneck from design to manufacture due to the multiple iterations and advanced physical behavior description in math. Thus, this paper presented a pattern-based design technology co-optimization (PB-DTCO) flow in cooperation with OPC to find out patterns which will negatively affect the yield and fixed it automatically in advance to reduce the run-time in OPC operation.
PB-DTCO flow can generate plenty of test patterns for model creation and yield gaining, classify candidate patterns systematically and furthermore build up bank includes pairs of match and optimization patterns quickly. Those banks can be used for hotspot fixing, layout optimization and also be referenced for the next technology node. Therefore, the combination of PB-DTCO flow with OPC not only benefits for reducing the time-to-market but also flexible and can be easily adapted to diversity OPC flow.
Beyond 40 nm technology node, the pattern weak points and hotspot types increase dramatically. The typical patterns for
lithography verification suffers huge turn-around-time (TAT) to handle the design complexity. Therefore, in order to
speed up process development and increase pattern variety, accurate design guideline and realistic design combinations
are required. This paper presented a flow for creating a cell-based layout, a lite realistic design, to early identify
problematic patterns which will negatively affect the yield.
A new random layout generating method, Design Technology Co-Optimization Pattern Generator (DTCO-PG), is
reported in this paper to create cell-based design. DTCO-PG also includes how to characterize the randomness and
fuzziness, so that it is able to build up the machine learning scheme which model could be trained by previous results,
and then it generates patterns never seen in a lite design. This methodology not only increases pattern diversity but also
finds out potential hotspot preliminarily.
This paper also demonstrates an integrated flow from DTCO pattern generation to layout modification. Optical
Proximity Correction, OPC and lithographic simulation is then applied to DTCO-PG design database to detect hotspots
and then hotspots or weak points can be automatically fixed through the procedure or handled manually. This flow
benefits the process evolution to have a faster development cycle time, more complexity pattern design, higher
probability to find out potential hotspots in early stage, and a more holistic yield ramping operation.
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