Mr. Hyungwon Yoo Profile

Hyungwon Yoo

at Hitachi High-Tech Korea Co Ltd

SPIE Involvement:

Author

Publications (4)

Proceedings Article | 10 April 2013 Paper

In-die overlay metrology method using defect review SEM images

Jaehyoung Oh, Gwangmin Kwon, Daiyoung Mun, Hyungwon Yoo, Sungsu Kim, Tae hui Kim, Minoru Harada, Yohei Minekawa, Fumihiko Fukunaga, Mari Nozoe

Proceedings Volume 8681, 868111 (2013) https://doi.org/10.1117/12.2010728

KEYWORDS: Overlay metrology, Scanning electron microscopy, Semiconducting wafers, Sensors, Image segmentation, Image processing, Error analysis, Measurement devices, Detection and tracking algorithms, Metrology

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Proceedings Article | 5 April 2012 Paper

Application of review-SEM to high-resolution inspection for 3xnm nodes

J. H. Oh, G. Kwon, D. Y. Mun, H. W. Yoo, Y. S. Choi, T. H. Kim, F. Fukunaga, S. Umehara, M. Nozoe

Proceedings Volume 8324, 83242P (2012) https://doi.org/10.1117/12.916244

KEYWORDS: Inspection, Image processing, Scanning electron microscopy, Defect detection, Sensors, Semiconductors, Image resolution, Bridges, Defect inspection, Image sensors

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Proceedings Article | 5 April 2012 Paper

CD-SEM and e-beam defect inspection of high-aspect ratio contact holes: measurement and simulation of precharge

S. Babin, S Borisov, G. Kwon, C. H. Lee, J. H. Oh, D. Y. Mun, H. W. Yoo

Proceedings Volume 8324, 832428 (2012) https://doi.org/10.1117/12.916441

KEYWORDS: Monte Carlo methods, Scanning electron microscopy, Defect inspection, Metrology, Particles, Sensors, 3D modeling, Inspection, Oxides, Optical simulations

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Proceedings Article | 2 April 2010 Paper

Process variation monitoring (PVM) by wafer inspection tool as a complementary method to CD-SEM for mapping field CDU on advanced production devices

Dae Jong Kim, Hyung Won Yoo, Chul Hong Kim, Hak Kwon Lee, Sung Su Kim, Koon Ho Bae, Hedvi Spielberg, Yun Ho Lee, Shimon Levi, Yariv Bustan, Moshe Rozentsvige

Proceedings Volume 7638, 76380B (2010) https://doi.org/10.1117/12.848699

KEYWORDS: Semiconducting wafers, Polarization, Line edge roughness, Critical dimension metrology, Wafer inspection, Process control, Metrology, Photomasks, Light scattering, Semiconductors

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As design rules shrink, Critical Dimension Uniformity (CDU) and Line Edge Roughness (LER) have a dramatic effect on printed final lines and hence the need to control these parameters increases. Sources of CDU and LER variations include scanner auto-focus accuracy and stability, layer stack thickness, composition variations, and exposure variations. Process variations, in advanced VLSI production designs, specifically in memory devices, attributed to CDU and LER affect cell-to-cell parametric variations. These variations significantly impact device performance and die yield. Traditionally, measurements of LER are performed by CD-SEM or OCD metrology tools. Typically, these measurements require a relatively long time to set and cover only selected points of wafer area. In this paper we present the results of a collaborative work of the Process Diagnostic & Control Business Unit of Applied Materials and Hynix Semiconductor Inc. on the implementation of a complementary method to the CDSEM and OCD tools, to monitor defect density and post litho develop CDU and LER on production wafers. The method, referred to as Process Variation Monitoring (PVM) is based on measuring variations in the scattered light from periodic structures. The application is demonstrated using Applied Materials DUV bright field (BF) wafer inspection tool under optimized illumination and collection conditions. The UVision^TM has already passed a successful feasibility study on DRAM products with 66nm and 54nm design rules. The tool has shown high sensitivity to variations across an FEM wafer in both exposure and focus axes. In this article we show how PVM can help detection of Field to Field variations on DRAM wafers with 44nm design rule during normal production run. The complex die layout and the shrink in cell dimensions require high sensitivity to local variations within Dies or Fields. During normal scan of production wafers local Process variations are translated into GL (Grey Level) values, that later are grouped together to generate Process Variation Map and Field stack throughout the entire wafer.

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