Metalenses are flat lenses made from thin films with sub-wavelength nano-optical structures that can be created using the same processes that have been developed for integrated circuit manufacturing. We present a workflow that simulates the manufacturing process and enables process engineers and optical designers to study the impact of manufacturing on metalens performance without waiting for multiple manufacture-and-test cycles. To demonstrate this workflow, we design several metalenses and characterize the impact of process variation on absolute focusing efficiency, transmission, and output electric field.
For leading edge technology node, many proximity effects during mask manufacturing process will change the mask details. Model-based Mask error correction (MEC) is needed for ensuring the mask fidelity. With the development of multi beam mask writers (MBMW), curvilinear mask offers many quality and performance advantages over Manhattan mask. It offers superior process window comparing to Manhattan mask for EUV process. In this paper, we discuss the results of model based curvilinear MEC based on Proteus platform. The quality and performance were compared between conventional compact model and Machine-Learning (ML) models. ML-based model can be accurately predicting mask printing signatures otherwise could not be predicted by convection compact model. Integrating MEC into Proteus platform offers seamless flow between different applications, like OPC, ILT and RET while preserve the device hierarchy.
Curvilinear OPC has been developed for improved process window, more freedom in mask constraint and better MRC enforcement. Combined Curve OPC with ILT can further improve mask synthesis flow. We demonstrate hybrid curve OPC/ILT flows for more flexible deployment. High NA OPC together with anamorphic MRC can be well handled in this platform. Curve OPC can be deployed in co-optimization flow like litho-etch OPC, process window aware OPC, etc. Correction of any angle layout is challenging. We present our OPC solutions in handle of any angle layout and demonstrate good correction results.
Generating test patterns with sufficient parameter space coverage has always been one of the critical steps towards
building good OPC models. The advancement in technology node requires continues updates to OPC modeling test
patterns. The traditional approach relies heavily on experiences gathered from older technology nodes. It often requires
rounds of costly test tape out. Here we propose an automated flow for test pattern generation utilizing a fast full chip
pattern matching algorithm. We describe the implementation of the flow. We also present experimental results and
discuss the benefit and challenges of the proposed flow.
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