Current applications of silicon photonic devices are strongly limited by waveguide performance. Rough sidewalls scatter electromagnetic radiation and lead to significant losses. Prototyping of state-of-the-art silicon photonic devices on full wafer scale requires maskless manufacturing. Therefore, variable shaped electron-beam lithography in chemically amplified photoresists and anisotropic etching processes are used. As a result, size and roughness errors in the photoresist structures are directly transferred to the silicon-waveguides. In this study a high-resolution chemically amplified negative photoresist for electron-beam writing was run in and optimized for photonic device manufacturing successfully. The investigation of the photoresist contrast and critical dimensions enabled the production of smooth and critical dimension stable lines in photoresist, which exhibit vertical sidewalls as well as a resolution limit far below 100 nm.
The choice of a staggered or coplanar geometry for organic thin-film transistors (TFT) has significant effects on the static and dynamic electronic properties of the transistors. Using two-port network analysis, we find that the parasitic capacitances and thus the unity current-gain (transit) frequencies are significantly more dependent on the gate-to-source overlap in the staggered TFTs than in coplanar TFTs, and that the transit frequency is higher overall when a coplanar geometry is implemented. We show that these differences are primarily attributed to the lower contact resistance in the coplanar TFTs (10 Ohm-cm) as well as smaller parasitic capacitances associated with the gate-to-contact overlaps.
A process for the fabrication of integrated circuits based on bottom-gate, top-contact organic thin-film transistors (TFTs) with channel lengths as short as 1 µm on flexible plastic substrates has been developed. In this process, all TFT layers (gate electrodes, organic semiconductors, source/drain contacts) are patterned with the help of high-resolution silicon stencil masks, thus eliminating the need for subtractive patterning and avoiding the exposure of the organic semiconductors to potentially harmful organic solvents or resists. The TFTs employ a low-temperature-processed gate dielectric that is sufficiently thin to allow the TFTs and circuits to operate with voltages of about 3 V. Using the vacuum-deposited small-molecule organic semiconductor 2,9-didecyl-dinaphtho[2,3-b:2’,3’-f]thieno[3,2-b]thiophene (C10 DNTT), TFTs with an effective field-effect mobility of 1.2 cm2/Vs, an on/off current ratio of 107, a width-normalized transconductance of 1.2 S/m (with a standard deviation of 6%), and a signal propagation delay (measured in 11-stage ring oscillators) of 420 nsec per stage at a supply voltage of 3 V have been obtained. To our knowledge, this is the first time that megahertz operation has been achieved in flexible organic transistors at supply voltages of less than 10 V. In addition to flexible ring oscillators, we have also demonstrated a 6-bit digital-to-analog converter (DAC) in a binary-weighted current-steering architecture, based on TFTs with a channel length of 4 µm and fabricated on a glass substrate. This DAC has a supply voltage of 3.3 V, a circuit area of 2.6 × 4.6 mm2, and a maximum sampling rate of 100 kS/s.
Extraordinary/Enhanced optical transmission (EOT) is studied in the realization of plasmonic based filters in the visible range and near infrared spectrum for the purpose of substituting the Bayer-pattern filter with a new CMOS-compatible filter which can be easily tuned to provide different filter spectra. The filters studied in this paper are based on nano-structured 150nm thick Aluminum (Al) layer sandwiched between silicon dioxide (SiO2) layers. The resonance wavelengths achieved by the filters are at 700nm and 950 nm. Three parameters are used for tuning the two filters, i.e., aperture area, the period, and the holes arrangement (square or rhombic lattice). The filter is based on the principle of surface plasmon polaritons (SPPs), where the electromagnetic waves of the incident light couples with the free charges of the metal at the metal-dielectric interface. EOT is observed when the metal is structured with apertures such as rectangular, circular, cross, bowtie, etc. The resonance frequency in that case depends on the shape of the aperture, material used, the size of the apertures, the period of the array, and the surrounding material. The fabricated two filters show EOT at wavelengths as designed and simulated with blueshift in the peak location.
Organic electronics are gaining increasing interest and attention in electronic device fabrication due to cost advantages
and low process manufacturing temperatures, which allow the use of mechanically-flexible polymeric substrates.
Different patterning techniques for Organic Thin Film Transistors (OTFT) with sub μm channel length are currently
under investigation like inkjet-printing, nanoimprint, optical- and e-beam lithography. This paper describes a new
approach for OTFT fabrication by device patterning with Si stencil lithography. This high resolution shadow mask
technique allows the parallel patterning of sub μm features without the use of photosensitive resists or chemical solvents,
which could lead to a degradation of the sensitive organic semiconductor layer. At first the device pattern is etched into a
thin Si membrane layer, creating design-specific sub μm features. Subsequent this stencil mask is aligned and clamped to
the substrate and material is deposited through the stencil apertures forming the desired device pattern onto the substrate.
By repeating this sequence with different deposition materials a classical top contact TFT architecture with a gate
electrode, gate dielectric, organic semiconductor and source drain contacts can be achieved.
HDRC (high dynamic range CMOS) allows for more than 120 dB signal range in image processing. Scene details with
both very high and extremely low radiant flux may thus appear within the same image. Color constancy over the entire
signal range and good high speed performance are further aspects of this logarithmic imager technology. These features
qualify HDRC cameras for thermography, since the signal range of Planck's temperature radiation in a two dimensional
array is comparable to HDRC's intensity range. Especially in material welding and laser cutting processes, in high power
light sources and in high temperature material processing, fast monitoring of the spacial and dynamic temperature
distributions present a challenge to conventional thermal imaging and thus call for innovative concepts. A particular
challenge is in the compensation of the emissivity of the radiating surface.
Here, we present a new concept based on a modified HDRC VGA color camera, allowing for visualization and
measurement of temperatures from about 800 °C up to 2300 °C. The modifications include an optical filter for
minimizing UV and IR straylight and a notch filter for clipping off the green optical range in order to separate the blue
and red RGB regions. An enhanced and adapted software provides a division of the neighboured red and blue pixel
signals by means of simply subtracting the HDRC signals. As a result the local temperature information of the
visualized scene spot is independent of emissivity.
This is, to our knowledge, the first demonstration of a high speed thermal imager to date.
Direct spray coating, a new photoresist deposition technique, is investigated to evaluate its potential for pattern transfer on wafers with very large topography. An Electronic Vision EV101 spray coating system is employed and AZ4823 photoresist is selected to form a thick layer of resist on flat wafers and to produce sufficient coverage on wafers with deep cavities. The dependence of the resist thickness on the dispensed volume of the resist is studied. A few key parameters are optimized to achieve a uniform resist layer. Special attention is paid to the layer characteristics when sprayed on wafers with cavities of various depths. A few applications of spray coating are shown to further illustrate its possibilities in MEMS.
An IC-compatible process for pattern transfer in deep wells and cavities for the integration of RF components is presented. After an anisotropic wet etching step used to define the optimum position of the ground plane, structures need to be patterned on the bottom of 250-400 micrometers dep etched grooves, trenches or cavities to realize wafer- through contact holes and metal patterns. Thick positive photoresist such as AZ4562 and ma-P275 are used. Modified resist spinning procedure and soft bake process resulted in a good coverage of the etched cavities, even for the deeper ones. The effect of resist thickness and spinning procedure on coating defect density and resolution loss is investigated and optimum conditions are found. A few examples of structures realized using the process described here are shown to indicate the potential and restrictions of this process.
The synchrotron x ray lithography (XRL) project described was conducted as a learning and feasibility vehicle for gate level lithography in support of IBM's most advanced CMOS logic programs. An electrically probable multilevel lithography test site was developed and characterized to exercise critical design, mask manufacture, alignment, exposure, and metrology issues in the 150 - 350 nm linewidth range. A fully capped silicided polysilicon gate stack was chosen for the electrical measurements in order to develop and demonstrate the XRL and related reactive ion etch process on a realistic, product-like substrate. This paper addresses test site design issues, elaborates on the mask manufacturing process, and presents SEM and electrical data from wafers processed at IBM's Advanced Semiconductor Technology Center. The data presented demonstrate the feasibility of supporting early device development and process integration with XRL and highlight the need for high resolution, defect free, proximity corrected masks to fully exploit the capabilities of x ray lithography.
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