KEYWORDS: Photomasks, Critical dimension metrology, Semiconducting wafers, Manufacturing, Scanning electron microscopy, Error analysis, Semiconductors, Process control, Lithography, Control systems
In the process of semicondutcor fabrication the translation of the final product requirements into specific targets for each component of the manufacturing process is one of the most demanding tasks. This involves the careful assessment of the error budgets of each component as well as the sensible balancing of the costs implied by the requirements. Photolithographic masks play a pivotal role in the semiconductor fabrication. This attributes a crucial role to mask error budgeting within the overall wafer production process. Masks with borderline performance with respect to the wafer fabrication requirements have a detrimental effect on the wafer process window thus inducing delays and costs. However, prohibitively strict mask specifications will induce large costs and delays in the mask manufacturing process. Thus setting smart control mechanisms for mask quality assessment is highly relevant for an efficient production flow. To this end GLOBALFOUNDRIES and the AMTC have set up a new mask specification check to enable a smart ship to control process for mask manufacturing. Within this process the mask CD distribution is checked as to whether it is commensurable with the advanced dose control capabilities of the stepper in the wafer factory. If this is the case, masks with borderline CD performance will be usable within the manufacturing process as the signatures can be compensated. In this paper we give a detailed explanation of the smart ship control approach with its implications for mask quality.
The continuing downscale of semiconductor fabrication ground rule requires increasingly tighter overlay tolerances, which becomes very challenging at the cutting-edge lithographic node. We need to keep improving overlay performance to admit the requirements of tight overlay budget. The conventional method of overlay control is controlling linear model parameters during alignment and process correction by APC (Advanced Process Control) for linear errors after alignment. Due to this kind of control for linear parameters, this linear error proportion out of total overlay error can be the indicator how well the overlay is being controlled by the conventional overlay control method. After achieving this small proportion of linear error, normally 10 parameters, out of total overlay errors, this conventional method of overlay control face the limitation of improvement and this implies us that it is necessary to work on non-linear overlay error for further improvement. Initial investigation starts from finding out contribution of grid and field for the remained error after 10 parameter linear modeling and the result shows up higher contribution from grid factor. The way to break down grid residual error is by method of control. Nikon provided GCM (Grid Compensation Matching) function which has some options to deal with these non-linear errors, so we tested and simulated a couple of new methods of overlay control to improve the other proportion of total overlay error beside linear overlay error. 1st approach for further improvement was remaining x,y offset feedback through APC for each field after linear modeling and 2nd was non-linear alignment and 3rd is the combination of both methods. This paper will explain which method will improve which part of overlay errors and the test or simulated results of improvement.
This paper discusses a variety of issues encountered in 193nm lithography high volume production. In order to debug the new 193nm technology, a layer from an older qualified technology was qualified on the new tools. Tool statistics were benchmarked against the installed 248nm tool base. Several issues not known from 248nm lithography or from low volume R&D type pilot runs on 193nm were uncovered. Specifically, issues related to aging of optical parts, defects from various sources, track processing, and masks are discussed.
CD control is crucial to maximize product yields on 300mm wafers. This is particularly true for DRAM frontend lithography layers, like gate level, and deep trench (capacitor) level. In the DRAM process, large areas of the chip are taken up by array structures, which are difficult to structure due to aggressive pitch requirements. Consequently, the lithography process is centered such that the array structures are printed on target. Optical proximity correction is applied to print gate level structures in the periphery circuitry on target. Only slight differences of the different Zernike terms can cause rather large variations of the proximity curves, resulting in a difference of isolated and semi-isolated lines printed on different tools. If the deviations are too large, tool specific OPC is needed. The same is true for deep trench level, where the length to width ratio of elongated contact-like structures is an important parameter to adjust the electrical properties of the chip. Again, masks with specific biases for tools with different Zernikes are needed to optimize product yield. Additionally, mask making contributes to the CD variation of the process. Theoretically, the CD deviation caused by an off-centered mask process can easily eat up the majority of the CD budget of a lithography process. In practice, masks are very often distributed intelligently among production tools, such that lens and mask effects cancel each other. However, only dose adjusting and mask allocation may still result in a high CD variation with large systematical contributions. By adjusting the illumination settings, we have successfully implemented a method to reduce CD variation on our advanced processes. Especially inner and outer sigma for annular illumination, and the numerical aperture, can be optimized to match mask and stepper properties. This process will be shown to overcome slight lens and mask differences effectively. The effects on lithography process windows have to be considered, nonetheless.
Overlay budgets are getting tighter within 300 mm volume production and as a consequence the process effects on alignment and off-line metrology becomes more important. In a short loop experiment, with cleared reference marks in each image field, the isolated effect of processing was measured with a sub-nanometer accuracy. The examined processes are Shallow Trench Isolation (STI), Tungsten-Chemical Mechanical Processing (W-CMP) and resist spinning. The alignment measurements were done on an ASML TWINSCANT scanner and the off-line metrology measurements on a KLA Tencor. Mark type and mark position dependency of the process effects are analyzed. The mean plus 3 (sigma) of the maximum overlay after correcting batch average wafer parameters is used as an overlay performance indicator (OPI). 3 (sigma) residuals to the wafer-model are used as an indicator of the noise that is added by the process. The results are in agreement with existing knowledge of process effects on 200 mm wafers. The W-CMP process introduces an additional wafer rotation and scaling that is similar for alignment marks and metrology targets. The effects depend on the mark type; in general they get less severe for higher spatial frequencies. For a 7th order alignment mark, the OPI measured about 12 nm and the added noise about 12 nm. For the examined metrology targets the OPI is about 20 nm with an added noise of about 90 nm. Two different types of alignment marks were tested in the STI process, i.e., zero layer marks and marks that were exposed together with the STI product. The overlay contribution due to processing on both types of alignment marks is very low (smaller than 5 nm OPI) and independent on mark type. Some flyers are observed fot the zero layer marks. The flyers can be explained by the residues of oxide and nitride that is left behind in the spaces of the alignment marks. Resist spinning is examined on single layer resist and resist with an organic Bottom Anti-Reflective Coating (BARC) underneath. Single layer resist showed scaling on unsegmented marks that disappears using higher diffraction orders and/or mark segmentation. Resist with a planarizing BARC caused additional effects on the wafer edge for measurements with the red laser signal. The effects disappear using the green laser of ATHENAT.
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