Shrinking feature sizes and the need for tighter CD (Critical Dimension) control require the introduction of new
technologies in mask making processes. One of those methods is the dose assignment of individual shots on VSB
(Variable Shaped Beam) mask writers to compensate CD non-linearity effects and improve dose edge slope. Using
increased dose levels only for most critical features, generally only for the smallest CDs on a mask, the change in mask
write time is minimal while the increase in image quality can be significant. However, this technology requires accurate
modeling of the mask effects, especially the CD/dose dependencies. This paper describes a mask model calibration flow
for Mask Process Correction (MPC) applications with shot dose assignment.
The first step in the calibration flow is the selection of appropriate test structures. For this work, a combination of linespace
patterns as well as a series of contact patterns are used for calibration. Features sizes vary from 34 nm up to
several micrometers in order to capture a wide range of CDs and pattern densities. After mask measurements are
completed the results are carefully analyzed and measurements very close to the process window limitation and outliers
are removed from the data set.
One key finding in this study is that by including patterns exposed at various dose levels the simulated contours of the
calibrated model very well match the SEM contours even if the calibration was based entirely on gauge based CD
values. In the calibration example shown in this paper, only 1D line and space measurements as well as 1D contact
measurements are used for calibration. However, those measurements include patterns exposed at dose levels between
75% and 150% of the nominal dose. The best model achieved in this study uses 2 e-beam kernels and 4 kernels for the
simulation of development and etch effects. The model error RMS on a large range of CD down to 34 nm line CD is
0.71 nm.
The calibrated model is then used to generate 2D contours for line ends, space ends and contacts and those contours are
compared to SEM images. For all patterns, including those very close to the resolution limit, very good contour overlay
is achieved. It appears that by including the various dose levels in the calibration a very good separation of the e-beam
model components from the etch components is possible and that this also results in very accurate 2D model quality.
In conclusion, very accurate mask model calibration is achieved for mask processes using shot dose assignment.
Standard test patterns can be used for calibration if they include the dose variations intended for correction.
A methodology is described wherein a calibrated model-based ‘Virtual’ Variable Shaped Beam (VSB) mask writer
process simulator is used to accurately verify complex Optical Proximity Correction (OPC) and Inverse Lithography
Technology (ILT) mask designs prior to Mask Data Preparation (MDP) and mask fabrication. This type of
verification addresses physical effects which occur in mask writing that may impact lithographic printing fidelity
and variability. The work described here is motivated by requirements for extreme accuracy and control of
variations for today’s most demanding IC products. These extreme demands necessitate careful and detailed
analysis of all potential sources of uncompensated error or variation and extreme control of these at each stage of
the integrated OPC/ MDP/ Mask/ silicon lithography flow. The important potential sources of variation we focus on
here originate on the basis of VSB mask writer physics and other errors inherent in the mask writing process. The
deposited electron beam dose distribution may be examined in a manner similar to optical lithography aerial image
analysis and image edge log-slope analysis. This approach enables one to catch, grade, and mitigate problems early
and thus reduce the likelihood for costly long-loop iterations between OPC, MDP, and wafer fabrication flows. It
moreover describes how to detect regions of a layout or mask where hotspots may occur or where the robustness to
intrinsic variations may be improved by modification to the OPC, choice of mask technology, or by judicious design
of VSB shots and dose assignment.
In this paper we discuss the EUV OPC modeling challenges and potential solutions, as well as OPC integration
requirements to support the forthcoming application of EUV lithography. 10-nm-node OPC modeling is considered as
an example. Wafer and mask process data were collected for calibration and verification patterns, to understand the
mask making error/OPC model interactions. Several factors, including compact mask topography modeling impact, were
analyzed by means of rigorous simulations and model fitting. This was performed on a large-scale data set, to ensure
accurate characterization of the OPC modeling strategies, using a large number of patterns.
KEYWORDS: Photomasks, Metals, Reliability, Semiconducting wafers, Extreme ultraviolet, Line edge roughness, Dielectric breakdown, Backscatter, Lithography, Back end of line
When compared to conventional chrome absorber masks, electron beam patterning of EUV masks requires additional
corrections to account for intermediate range electron backscattering from the mirror and tantalum based absorber layers. The performance of this Mask Proximity Correction software should not be specified based solely on traditional mask linearity measures. We propose a new mask linearity specification based on Time Dependent Dielectric Breakdown requirements for metal layers.
The 50keV ebeam exposure of EUV blanks leads to additional electron backscattering from the tantalum layer and the
mirror portion of the blank substrate that cannot be adequately corrected by in-tool algorithms. Coupling this additional
backscatter with process effects, such as develop and etch micro/macro loading, results in significant systematic Critical
Dimension (CD) errors for through pitch and linearity patterns on EUV masks. In wafer production EUV masks are
targeted as single layer exposure, which requires extremely stringent CD control. The systematic CD errors can easily
exceed the CD requirements of a typical EUV mask, facilitating the need for a correction scheme or mask process
correction (MPC).
AMTC and GLOBALFOUNDRIES have started a program to evaluate MPC solutions and drive improvements.
Working closely with companies that provide solutions for ebeam and process modelling along with the corresponding
correction, we have completed several iterations of MPC evaluations. Specifically, we have tested different equipment,
processes and process partitioning for model calibration including a verification of the results.
We report on the results of these evaluations, which include simulation of available models, as well as verification data
from mask prints. We conclude by summarizing the current capabilities of available MPC solutions and present the
remaining gaps for model and correction accuracy as well as the remaining questions for fully implementing MPC into
the process landscape.
Several methods are evaluated to improve the accuracy of extreme ultraviolet (EUV) lithography OPC models by including additional physical effects which are not commonly used in deep ultraviolet (DUV) OPC. The primary additions to the model in this work are model based corrections for flare and two different corrections for mask shadowing effects, commonly referred to as HV bias. The quantitative, incremental, improvement from each of these additions is reported, and the resulting changes in tape-out flow and OPC runtime are discussed
KEYWORDS: Photomasks, Optical proximity correction, Data modeling, Calibration, Data conversion, Point spread functions, Manufacturing, Extreme ultraviolet, Process modeling, Semiconducting wafers
When compared to conventional chrome absorber masks, electron beam patterning of EUV masks requires additional
corrections to account for electron backscattering from the mirror and tantalum (Ta) based absorber layers. Current ebeam systems cannot correct for these additional backscattering effects with in-tool proximity effect correction (PEC)
algorithms. Hence new methods of correction are needed, which require an implementation of the correction into the
mask writer data prior to exposure. Where these corrections should be performed in the data flow between mask user and mask supplier, and who should calibrate and maintain the corrections is not clear. We present various approaches for model calibration as well as discuss the possible options for inserting mask process correction (MPC) into the mask process landscape. We report on an attempt to calibrate a correction for EUV masks using actual CD data, and an e-beam backscattering model. The resulting Point Spread Functions (PSF) were used to simulate and predict the measured CD data. We also explored the robustness of these models by varying the writing tool and mask blank characteristics. We conclude by recommending an appropriate flow for calibration and use of mask process correction and ownership of the model calibration, maintenance and the data correction processes.
Although the k1 factor is large for extreme ultraviolet (EUV) lithography compared to deep ultraviolet (DUV)
lithography, OPC is still needed to print the intended patterns on the wafer. This is primarily because of new
non-idealities, related to the inability of materials to absorb, reflect, or refract light well at 13.5nm, which must
be corrected by OPC. So, for EUV, OPC is much more than conventional optical proximity correction. This work
will focus on EUV OPC error sources in the context of an EUV OPC specific error budget for future technology
nodes. The three error sources considered in this paper are flare, horizontal and vertical print differences, and
mask writing errors. The OPC flow and computation requirements of EUV OPC are analyzed as well and
compared to DUV. Conventional optical proximity correction is simpler and faster for EUV compared to DUV
because of the larger k1 factor. But, flare and H-V biasing make exploitation of design hierarchy more difficult.
REBL (Reflective Electron Beam Lithography) is being developed for high throughput electron beam direct write
maskless lithography. The system is specifically targeting 5 to 7 wafer levels per hour throughput on average at the
45 nm node, with extendibility to the 32 nm node and beyond. REBL incorporates a number of novel technologies
to generate and expose lithographic patterns at estimated throughputs considerably higher than electron beam
lithography has been able to achieve as yet. A patented reflective electron optic concept enables the unique
approach utilized for the Digital Pattern Generator (DPG). The DPG is a CMOS ASIC chip with an array of small,
independently controllable cells or pixels, which act as an array of electron mirrors. In this way, the system is
capable of generating the pattern to be written using massively parallel exposure by ~1 million beams at extremely
high data rates (~ 1Tbps). A rotary stage concept using a rotating platen carrying multiple wafers optimizes the
writing strategy of the DPG to achieve the capability of high throughput for sparse pattern wafer levels. The
exposure method utilized by the DPG was emulated on a Vistec VB-6 in order to validate the gray level exposure
method used in REBL. Results of these exposure tests are discussed.
Two of the key performance parameters in the manufacture of photomasks and reticles are composite placement and composite overlay. Multipoint fitting of the placement and overlay errors is typically used in specifying the performance of the printing tool, whereas two-point fitting is more commonly used in the mask-production environment. In this study, Monte Carlo simulation techniques are used to compare the placement results that may be expected using the two methods. Mask yields are evaluated sing the maximum observed error as the primary metric, because this criterion is prevalent in the industry. The influence of several factors is examined, including number of sample points, size of test pattern, and the presence of systematic printing errors. The baseline test case consists of a 7 X 7 grid of points with an extent of 132-nm square with two additional alignment marks separated in the x direction by 144 mm, and random normally distributed errors with standard deviation (sigma) . For this case, the expected maximum error at 95% mask yield from a two-point alignment is approximately 4.5 (sigma) , and (tau) equals 1.3, where (tau) is defined as the ratio of the maximum error for two-point versus multipoint fitting. The expected maximum error depends logarithmically on the number of sample points, and (tau) decreases as the number of points increases. A sinusoidal systematic error in the printing system greatly degrades the yield using two-point alignment but has relatively little effect upon the yield using multipoint alignment. Similarly, an orthogonality mismatch between the printing and metrology tool causes (tau) to increase significantly, whereas a scale mismatch decreases (tau) . It is also demonstrated that the result from two-point alignment has more statistical uncertainty than that from the multipoint methodology, and thus multipoint alignment is more accurate in determining the expected performance of a given printing system from a limited set of sample masks.
Performance data from a prototype 50 kV shaped electron-beam (e-beam) pattern generator is presented. This technology development is targeted towards 180-130 nm device design rules. It will be able to handle 1X NIST X-ray membranes, glass reduction reticles, and 4- to 8-inch wafers. The prototype system uses a planar stage adapted from the IBM EL-4 design. The electron optics is an 50 kV extension of the AEBLE%+TM) design. Lines and spaces of 0.12 micrometers with < 40 nm corner radius are resolved in 0.4 micrometers thick resist at 50 kV. This evolutionary platform will evolve further to include a new 100 kV column with telecentric deflection and a 21-bit (0.5 mm) major field for improved placement accuracy. A unique immersion shaper, faster data path electronics, and 15-bit (32 micrometers ) minor field deflection electronics will substantially increase the flash rate. To match its much finer address structure, the pattern generator figure word size will increase from 80 to 96 bits. The data path electronics uses field programmable gate array (FPGA) logic allowing writing strategy optimization via software reconfiguration. An advanced stage position control (ASPC) includes three-axis, (lambda) /1024 interferometry and a high bandwidth dynamic corrections processor (DCP). Along with its normal role of coordinate transformation and dynamic correction of deflection distortion, astigmatism, and defocus; the DCP improves accuracy by modifying deflection conditions and focus according to measured substrate height variations. It also enables yaw calibration and correction for Write-on-the FlyTM motion. The electronics incorporates JTAG components for built-in self- test (BIST), as well as syndrome checking to ensure data integrity. The design includes diagnostic capabilities from offsite as well as from the operator console. A combination of third-party software and an internal job preparation software system is used to fracture patterns. It handles tone reversal, overlap removal, sizing, and proximity correction. Processing of large files in a commercial mask shop environment is made more efficient by retaining hierarchy and using parallel processing and data compression techniques. Large GDSIITM and MEBES data files can be processed. Data includes timing benchmarks for a 1 Gbit DRAM on both proximity and reduction reticles. The paper presents 50 kV results on silicon and quartz substrates along with examples of overlay to an external grid, field butting, and critical dimension (CD) control data. Selective experiments testing system stability, calibration accuracy, and local correction software implementation on a VAX control computer are also given.
Lithography systems for sub-0.25micrometers designs will probably require masks with very high data content, small feature sizes, and extreme accuracies. Moreover, the mask substrates themselves will probably be exotic, compared with today's quartz blanks. We examine the requirements set forth in wafer lithography technology roadmaps and the published characteristics for proposed lithography tools to extrapolate to the mask pattern generation requirements. We then examine the implications for the maskmaking tools in the year 2000. These requirements lead to a discussion of the Etec Excalibur e-beam mask writer program. Finally, we comment on the prospects of an e-beam direct write technology applicable to the year 2000 production requirements and discuss the potential of some architectures proposed in the literature. We intend to show why radical innovation will be required above and beyond what has been disclosed to date.
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