Large window-size membranes for stencil masks are required to increase the throughput of electron projection lithography (EPL) and low-energy electron projection lithography (LEEPL). In this paper, image placement (IP) accuracy and methodology for correcting stress-induced distortions on 4 X EPL masks are addressed. Although the average of local IP errors (| mean | + 3σ) for reference features across an entire 1mm-window EPL mask is 13.4 nm, the average of errors across an entire 4mm-window EPL mask increases to 20.4 nm, which could be reduced to the required budget with further study on EB writing accuracy or IP corrections. In addition we evaluate local IP errors on 4mm-window mask due to pattern gradients by measuring the placement errors at the edge of dense hole arrays. Applying the correction for stress-induced distortions to EB data, we can reduce the placement errors for dense features to 4.6 nm, which is less than the 10 nm budget allocated for 4mm-window EPL mask at the half-pitch features of 45 nm node. For the global IP, only the measurement repeatability of 7.8 nm contributes to the global IP budget measuring all the global position over an entire 4mm-window EPL mask. And we can meet the required global IP budget. Finally, IP accuracy for a single membrane is also presented, showing the IP error is 24.5 nm (| mean | + 3σ), which compares with that of COSMOS type LEEPL mask. Methodology of measuring the position data on a single membrane, however, remains to be developed.
We manufactured LEEPL masks for 65-nm node and evaluated the masks for the critical dimension (CD), image placement (IP) and defects. Although the CD uniformity was 8.0 nm (3σ), an improvement is promising by resist upgrading. The CD linearity was within 5 nm (3σ) through the range of 80- to 300-nm width and the 65-nm hole patterns were successfully resolved. The local and global IP errors obtained were 23.2/16.4 nm and 8.76/6.66 nm (in the x/y directions), respectively. A defect inspection was conducted and detected defects were classified. Most of the defects were miss-placement and miss-size, which seemed to be non-killer defects. On the other hands, foreign materials that must be killer defects were analyzed using energy dispersion X-ray (EDX) and found that they consist of Si. Si fragments mainly came from strut walls and by employing new backside-etching conditions, we improved roughness of strut walls. As a result, no closed defects were detected.
Two types of strut-supported low energy electron-beam proximity projection lithography (LEEPL) masks which are grid-type mask and COSMOS-type mask, were investigated for Global image placement (IP). First, we evaluated the dynamic repeatability measurement performance for global IP, measuring a same mask 10 times on a 46 x 46 mm pattern area by using LEEPL electrostatic chuck (ESC). The measurement repeatability for grid type and COSMOS type were 5.1/7.8 nm and 4.4/5.8 nm in x/y directions respectively. And then global in-plane distortion (IPD) of COSMOS type masks with various stress and flatness were measured. The global IPD of a COSMOS-type mask with a low stress of 10 MPa and a flatness of 3.1 μm was 6.5/6.4 nm in x/y directions, which is negligible assuming the measurement repeatability. Finally the global IPs of the two-type masks were measured. The global IPs for the grid-type and COSMOS-type were 24.5/15.7 nm and 23.2/16.4 nm in x/y directions respectively. Thus we confirmed that the global IP obtained meet the required value of less than 30 nm.
A production-compatible method for the correction of image-placement (IP) error over a 1x stencil mask as used for proximity electron lithography (PEL) has been demonstrated. The mask IP error as measured using a newly developed metrology tool was fed forward to the PEL stepper, LEEPL-3000 and corrected for via the fine deflection of the electron beam. The overlay errors with respect to the substrate patterned by the ArF scanner have decreased from 63.6/59.3 nm to 26.1/36.4 nm in the x/y directions, but they are still larger than the errors of 15.2/14.8 nm for the conventional feedback method. Therefore, some improvements in the metrology method, the mask chucking method, the mask flatness and so on are required.
We report the first evaluation results for the printability and detectability of mask defects on a 1x stencil mask as used for proximity electron lithography (PEL). The defect printability has been defined for the patterns after the multi-step etching process through the tri-layer resist system inherently required for the use of low-energy electrons and the substrate. According to the three-dimensional lithography simulation, this definition is preferable to the conventional one based on the resist patterns prior to the etching process in the point that smoothing effects on defects are automatically taken into account. The critical size of printable defects as defined is 22 nm for 140 nm contact holes, while the stringent value of 16 nm is predicted in the conventional definition. Also, the detectability of the printable defects has been assessed by using the transmission electron-beam (EB) inspection tool. The assessment has been performed for both programmed defects and real defects occurred in contact-hole arrays. For the programmed defects, the perfect repeatability has been demonstrated for all the defects with printable sizes. In addition, real defects with the size of 15 nm have been successfully detected in the contact-hole arrays. Therefore, this study has demonstrated the manufacturability of PEL masks from the viewpoint of defect inspection.
The performance of the LEEPL production tool is discussed from the framework of the litho-and-mask concurrent development schemes to establish the feasibility of proximity electron lithography (PEL) especially for contact and via layers in the 65-nm technology node. The critical-dimension (CD) uniformity of 4.7 nm has been achieved for 90-nm contact holes over the 1x stencil mask. Thus, the mask patterns can be transferred onto the resist layer with CD errors of less than 10%, even if the mask-error enhancement factor (MEEF) of 1.6 is taken into account. The mask manufacturability is improved if the MEEF further decreases via the use of thinner resists. Meanwhile, the overlay accuracy of 21.1 nm has been achieved in mix-and-match with the ArF scanner, with the intra-field error of only 5.1 nm owing to the real-time correction for the mask distortion. Also, the conditions for splitting dense lines into two complementary portions have been determined to avoid the pattern collapse in wet-cleaning and drying processes. The critical length of 2 mm is fairly safe for 70-nm lines if the low-damage drying is employed. The inspection tool based on transmission electron images cannot detect all printable defects without further optimization, hence a future challenge.
We have prepared 100-mm and 200-mm 1X stencil masks for low energy electron-beam proximity projection lithography (LEEPL) using silicon on insulator (SOI) substrates. We chose 200-mm without frame type format for production mask and 100-mm with NIST-like frame type for developing. And we employed COSMOS (complementary stencil masks on strut-supports) structure proposed by SONY to suppress in-plane distortion (IPD) of membrane. Our 100-mm mask contains 70-nm node device patterns. The critical dimension (CD) uniformity of a 100-nm width line patterns was 5.6 nm in range within 20-mm square area. The CD linearity of the line patterns was 5.5 nm in range throughout the range of 80- to 300-nm width. In our 200-mm mask, 100-nm width line patterns and 150-nm width hole patterns were successfully fabricated within 46-mm square area.
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