Based on either a SOI wafer or a bulk-silicon wafer, we discuss silicon photonic devices and integrations for chip-level
optical interconnects. We present the low-voltage silicon PICs on a SOI wafer, where Si modulators and Ge-on-Si
photodetectors are monolithically-integrated for intra-chip or inter-chip interconnects over 40 Gb/s. For future chip-level
integration, the 50 Gb/s small-sized depletion-type MZ modulator with the vertically-dipped PN-depletion-junction
(VDJ) is also presented. We report vertical-illumination-type Ge photodetectors on bulk-silicon wafers, with high
performances up to 50 Gb/s. We present the bulk-silicon platform for practical implementation of chip-level
interconnects, and the performance of the photonic transceiver silicon chip.
A spacer patterning technique using a poly-Si micro-feature and a SiO2 spacer has been demonstrated to achieve sub-22
nm structures with conventional semiconductor equipments. The sub-22 nm structures have been fabricated by a plasma
etching of Si substrate with a spacer oxide mask of which dimension is accurately controlled by the deposited film
thickness. The profile of the Si nano-feature was influenced by an O2 flow rate during Si etching in inductively coupled
plasma (ICP). As the O2 flow rate was decreased, the etch profile was improved vertically even though the etch rate of Si
was slightly decreased. We obtained a 6-inch Si template with both nano- and micro-features of positive shape used for a
master mold in nanoimprint lithography (NIL). The nano-sized Si features showed 22-nm width and 145-nm height with
the slope of 87°. Further size reduction by anisotropic wet etching with KOH solution was also investigated.
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