In this work we studied the impact of stochastic resist defects on electrical measurements of BEOL structures, and seek to demonstrate that large electrical test structures, built with a relatively simple patterning flow, can be used in the early stages of resist, and patterning development, as the electrical failures are almost exclusively caused by resist defects. To that end, single-layer electrically testable metal patterns at minimum metal pitch of 28nm were created using a single 0.33NA-EUV exposure and a metal damascene process flow. A bright field mask was exposed with a metal-organic, negative-tonedevelopment resist process to create trench structures that are transferred into an oxide dielectric layer. Following this, the trenches were filled with ruthenium (Ru) for electrical testing of meander resistor and fork-fork structures.
EUV (extreme ultraviolet) lithography is progressively being inserted in high volume manufacturing of semiconductors to keep up with node shrinkage. However, defectivity remains one big challenge to address in order to be able to exploit its full potential. As in any type of lithographic process, processing failures and in-film particles are contributors that need to be reduced by the optimization of coating and development processes and improved dispense systems. On top of these defects, stochastic failures, due to photon shot noise or non-uniformities in the resist, are another major contribution to the defectivity. To support their mitigation, etch process can be used to avoid their transfer to underlying layers. However, it requires a sufficient resist mask thickness. For line and space patterns, providing more resist budget comes with a trade-off which is the increase of pattern collapse failures, especially with shrinking critical dimensions. Collapse mitigation approaches are therefore very important to enable tight pitches and were explored. Stack engineering and especially optimization of resist under layers will be crucial components to enable patterning and defect reduction of shrinking pitches. Finally, as an alternative to traditional chemically amplified resists, metal containing resists are also promising because of their inherent high etch resistance. Dedicated hardware and processes were developed the use of such materials and prevent metal contamination to other tools during further processing steps.
In this report will be presented the latest solutions to further decrease defectivity towards manufacturable levels and provide more process margin to achieve better quality patterning towards the limits of NA 0.33 EUV exposure. Furthermore, technologies to improve CD uniformity and stability, which are required for mass production, will also be reported.
For many years traditional 193i lithography has been extended to the next technology node by means of multi-patterning techniques. However recently such a 193i technology became challenging and expensive to push beyond the technology node for complex features that can be tackled in a simpler manner by the Extreme UltraViolet Lithography (EUVL) technology. Nowadays, EUVL is part of the high-volume manufacturing device landscape and it has reached a critical decision point where one can push further the single print on 0.33NA full field scanner or move to a EUV double patterning technology with more relaxed pitches to overcome current 0.33NA stochastic limits. In this work we have selected the 28nm pitch dense line-space (P28) as critical decision check point. We have looked at the 0.33NA EUV single print because it is more cost effective than 0.33NA EUV double patterning. In addition, we have conducted a process feasibility study as P28 in single print is close to the resolution limit of the 0.33NA EUV full field scanner. We present the process results on 28nm dense line-space patterning by using Inpria’s metal-oxide (MOx) EUV resist. We discuss the lithographic and etching process challenges by looking at resist sensitivity, unbiased line edge roughness (LER) and nano patterning failures after etching (AE), using broad band plasma (BBP) and e-beam (EB) defectivity inspection tools. To get further understanding on the P28 single patterning capability we have integrated the developed EUV MOx process in a relevant iN7 technology test vehicle by developing a full P28 metallization module with ruthenium. In such a way we were able to carry on electrical tests on metallized serpentine, fork-fork and tip-to-tip structures designed with a purpose of enabling further learning on pattern failures through electrical measurements. Finally, we conclude by showing the readiness of P28 single exposure using Inpria’s MOx process on a 0.33NA EUV full field scanner.
In this paper, we will investigate defect modes and pattern variations for EUV (extreme ultra-violet lithography) double pattering scheme using self-aligned litho-etch-litho-etch process on final pitch 28nm test structures. As we continuously shrink device sizes towards aggressive pitches, the industry is moving towards adopting double pattering using EUV. Although we continue to push limits of 0.33NA EUV in terms of pitch and CD (critical dimensions) with novel resists and processes, stochastic defects pose greater challenge at pitches below 40 nm [1]. One of the ways to circumvent this problem is to use a multi-patterning scheme with relaxed design rule. Self-aligned litho-etch-litho-etch (SALELE) is one such scheme for early BEOL (back end of line) layers. The benefit of this patterning approach is that no dummy metal is added and blocks are needed only at tight tip-to-tip definitions, which can help to reduce parasitic capacitance. In this paper we will employ SEM inspection techniques to understand pattern variabilities, after initial optical inspection was done to discover different defect modes. We show that with analysis of SEM images we can get further insight on process variations.
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