As technology nodes further shrink, high yield becomes more and more challenging to achieve. Photoresist resolution (see Figure 2) and CD uniformity are two core yield limiters. This can be improved with the use of Lam’s EUV dry photoresist system[1], where the dry develop technique is used to replace wet develop. This process is also less prone to pattern collapse[1]. Another advantage of this new photoresist system consists in its higher dose sensitivity compared to conventional photoresists which leads to higher throughput[1][2]. High resolution process needs to be combined with optical proximity correction (OPC) to enable cutting edge EUV patterning. OPC relies on the capability of a model to predict accurately the behavior of such an innovative process. The purpose of this study is to provide a comprehensive quantification and characterization of the accuracy of an OPC model fitted for this process ADI and AEI (after carbon open). We generated wafers exposed with an OPC calibration reticle, processed with Lam’s dry deposited and dry developed photoresist. The anchor is a horizontal line-space grating at pitch 32nm (Figure 2). We acquired CDSEM images of more than 1800 features ADI (after dry develop) and AEI (after carbon open). A subset of the features were collected through FEM ADI. To better understand the characteristics of the dry photoresist system, we used metrics such as proximity, MEEF, DoF and EL. ADI OPC models were calibrated using ASML Tachyon software. Finally, we evaluated the OPC model accuracy of both Tachyon FEM+ (physically motivated) and Newron (machine-learning) engines, ADI for pitch 32nm BEOL metal layer use case.
Extending 0.33 NA extreme ultraviolet single patterning to 28-nm pitch becomes challenging in stochastic defectivity, which demands high-contrast lithographic images. The low-n attenuated phase-shift mask (attPSM) can provide superior solutions for individual pitches by mitigating mask three-dimensional effects. The simulation and experiment results have shown substantial imaging improvements: higher depth of focus at similar normalized image log slope and smaller telecentricity error values than the best binary mask configuration. In this work, the exploration of low-n attPSM patterning opportunity for pitch 28-nm metal design is investigated. Using generic building block features, the lithographic performance of the low-n attPSM is compared with the standard binary Ta-based absorber mask. In addition, the impact of mask tone (bright field (BF) versus dark field) on the pattern fidelity and process window is evaluated both by simulations and experiments. The results indicate that BF low-n attPSM provides the best patterning performance. Consequently, the BF low-n attPSM patterning performance is assessed with an actual imec N3 pitch 28-nm random logic metal design. The wafer data indicate BF low-n attPSM enables good patterning fidelity, as well as good overall process window with high exposure latitude (∼20 % ).
Recent developments in multi-beam mask writers (MBMW)1 enable the manufacturing of curvilinear masks. This promises higher patterning accuracy on wafer. The increased patterning flexibility takes us into new territories for mask manufacturing accuracy, precision and Mask Rule Check (MRC). MBMW allows Optical Proximity Correction (OPC) to venture into Inverse Lithography Technology (ILT) solutions, enabling accurate curvilinear masks. New challenges are also encountered when building OPC models that target ILT masks, such as on wafer metrology and pattern coverage. This exploration will be the focus of this study, in particular the MRC and mask characterization aspects, leveraging a new curvilinear reticle available at imec. As a result of its fully curvilinear nature, conventional mask metrology – solely based on cutline CDs – is no longer entirely adequate. Therefore, a new metrology flow must be developed to assess and quantify mask errors, relying on mask SEM image contour extraction and Mask Edge Placement Error (MEPE) evaluations. Our proposed flow has three steps: -Mask CDSEM images are loaded into a software, which enables an accurate contour extraction and alignment to the original design. The output of this exercise is a design file with open contours. - The output design file is converted into polygons (i.e., defining inside/outside polygons areas) by utilizing the original design as a guide. This allows for full compatibility with the next stage. -Lastly, a highly-sampled MEPE is determined for all polygons, both from the main and assisting features. The result is then analyzed offline. Ultimately, this curvilinear mask data analysis sequence was used on several subsets of the mask metrology dataset. In order to validate the approach, we reproduced the CD based metrology provided by the mask shop. We then expanded our scope to parametric curvilinear features, to find correlators (i.e. local design properties) to the observed mask error observed (e.g., polygon local curvature or density). Finally, ILT clips were used to verify the determined correlators.
In order to improve logic via printing we propose staggered vias to effectively regularize randomly placed vias in a typical logic design. We accomplish this (i) by forcing via placement on a staggered sub-grid of the standard manhattan grid and (ii) by placing smaller fixed-size via Sub-Resolution Assist Features (SRAFs) on all remaining empty positions of the staggered grid. We devised a methodology to create such staggered via placement in a standard Place&Route (PNR) design flow and evaluated the concept on a 64-bit (64b) ARM core implementation through a PowerPerformance-Area (PPA) analysis. From a PNR run-time perspective and PPA analysis this looked a very viable implementation with little to no disadvantages compared to standard via placement. Finally, to experimentally test and compare staggered vias and against standard manhattan vias, we designed a via mask with both staggered and standard manhattan vias patterns and exposed them on an 0.33NA NXE3400 EUV lithography system. Analysis of experimental results on a 38nm via pitch show 40% smaller best-focus shift across the slit, and 20% smaller via-via CD variation for staggered vias compared to Manhattan vias with regular SMO.
On a Silicon Photonics integrated circuit, information is carried by the light that propagates within silicon waveguides. The waveguide’s geometry determines the functionality. The curvilinearity of Silicon Photonics designs would raise challenges for the manufacturability. However, so far Silicon Photonics design dimensions are considered relaxed by the industry. Also, the type of shapes that are drawn would generally use rather simple geometry objects. This allows the usage of conventional techniques in the different phases of the manufacturability. Recently has emerged a type of Silicon Photonics design, referred to as “inverse design”. This new technique produces designs that are very exotic and quite unpredictable. It shows complex geometries which critical dimensions require innovative Resolution Enhancement Techniques at the different stages of the Optical Proximity Correction flow. The success of these “inverse designs” relies on a very accurate pattern fidelity. This presentation will demonstrate a flow going from modelling, to OPC and metrology and verification of the manufactured wafer data. This flow permits to tackle the challenges brought newly to the Silicon Photonics environment.
Driving down imaging-induced edge placement error (EPE) is a key enabler of semiconductor technology node scaling1-3. From the 5 nm node forward, stochastic edge placement error (SEPE) is predicted to become the biggest contributor to total edge placement error. Many previous studies have established that LER, LCDU, and similar variability measurements require corrections for metrology artifacts and noise as well as mask variability transfer to more accurately represent wafer-level stochastic variability. In this presentation, we will discuss SEPE band behavior based on a methodology that allows local extraction of SEPE from total measured local variability (LEPU) in a generalized way along 2D contours.
With the adoption of extreme ultraviolet (EUV) lithography for high volume production in the advanced wafer manufacturing fab, defects resulting from stochastic effects could be one of major yield killers and draw increasing interest from the industry. In this paper, we will present a flow, including stochastic edge placement error (SEPE) model calibration, pattern recognition and hot spot ranking from defect probability, to detect potential hot spot in the chip design. The prediction result shows a good match with the wafer inspection. HMI eP5 massive metrology and contour analysis were used to extract wafer statistical edge placement distribution data.
KEYWORDS: Process modeling, OLE for process control, Optical proximity correction, SRAF, Semiconducting wafers, Scanners, Critical dimension metrology, Scanning electron microscopy, Process control, Finite element methods
As technology nodes shrink, OPC model accuracy needs to the fulfill tighter requirements. Those requirements can be met only under good process control. However, OPC model accuracy relies on the specific context. Ignoring the impact of process variation on OPC accuracy could lead to break edge placement error (EPE) budget. The OPC process monitoring project at imec is conducted on imec logic N7 M2 design at pitch 32nm use case and aims at quantifying long-term validity of the OPC model in the face of NXE:3400 scanner and process variations. To account and compensate for scanner and process variations impact, the ability of restoring OPC validity by OPC model dose tuning is tested.
The purpose of our study is to evaluate the benefit of contrast enhancement strategies on a logic metal layer at pitch 28 nm. We build up on three studies from imec and ASML [1][2][3]. We take as a reference a Negative Tone Development (NTD) Metal Oxide Resist (MOR) process used in combination with a binary TaBN mask absorber, without SRAF, exposed with an X/Y symmetric pupil on a 0.33 NA EUV scanner, the NXE:3400 from ASML [7]. The fading mitigation strategies leverage asymmetrical pupil (monopole), wavefront injection (Z6 aberration) and low-n attenuated Phase Shift Mask (PSM). We find very good agreement between our simulations on design clips, the theoretical expectations and the experimental data shared in the above mentioned papers on building blocks (L/S through pitch and dense tip-to-tip). Overall the three fading correction techniques are efficient to improve the printability of our use case in term of ILS. It also improves the best focus shift of L/S through pitch and between L/S and tip-to-tip. In conclusion, the most promising exposure strategy for the logic metal pitch 28 nm use case is the attenuated PSM. It provides the highest ILS, the narrower best focus range, the largest overlapping process window without any compromise on the illumination efficiency, i.e. using the full NXE:3400 throughput.
In this contribution we describe a simulation and experimental study investigating the impact of mask non-ideality and Mask Process Correction (MPC) model choices on Optical Proximity Correction (OPC) model accuracy for an EUV use case. We describe simulation flows and their results for two cases. In the first case we investigate the impact of using an MPC simulated mask contour vs an ideal post-OPC mask. In the second case we investigate the differences between simulations using experimentally measured and simulated mask contours. The wafer data used in this study is an N5 M2 process developed at IMEC with contour-based metrology performed using ASML MXP. NCS NDE-MPC models are created using POR CDSEM CD data and MXP contour data. OPC models are calibrated and evaluated using ASML FEM+ software.
Inpria has developed a directly patternable metal oxide hard-mask as a high-resolution photoresist for EUV lithography1. In this contribution, we describe a Tachyon 2D OPC full-chip model for an Inpria resist as applied to an N7 BEOL block mask application.
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