We present a camera system for instantaneous, non-destructive capture of spectral signatures for forensic analysis. Our
system detects highly probative samples in the forensic scene mixed by the multiple target objects by combining a coded
aperture snapshot spectral imager with a multi-spectral detection algorithm. An Adaptive Cosine Estimator (ACE) is
used to quantitatively detect and classify the probative samples from the decoded spectral datacube. In this paper, we
demonstrate selected results using our system for luminescence characteristics and spectral classification of a number of
samples.
KEYWORDS: Video, Video surveillance, Video compression, Computer programming, Boxcar filters, Commercial off the shelf technology, Surveillance, Information visualization, Video processing, Situational awareness sensors
We introduce Salience-Based Compression (SBC), a vision-guided pre-filtering technology, coupled with standardsbased
video coding. SBC works by detecting and tracking salient features and keeping them sharp; non-salient features
are lowpass filtered, causing an automatic and beneficial drop in bit rate. Because salience-based pre-filtering is
performed as a pre-processing step, it can interface to any COTS video encoder, thus enabling use in existing
infrastructures and ensuring the compliance of the video bitstream that is produced. For typical aerial surveillance video,
SBC can reduce bit rate by up to a factor of four, yet still provide full motion video (FMV) and preserve salient visual
information.
KEYWORDS: Digital signal processing, Computer programming, Video, Quantization, Motion estimation, Video coding, Video surveillance, Video compression, Profiling, Signal processing
In this paper, we present the work on implementation of a half-D1interlaced MPEG-4 encoder with Equator Technology DSP chip, BSP-15. The BSP-15 DSP consists mainly of a VLIW core, Co-processors, and media I/O interfaces. The encoder utilizes several BSP-15 functional blocks in parallel. In general, the VLIW performs pixel procesing that is computationally intensive. The VLx coprocessor completes variable length coding. Further parallelism is obtained by pre-loading data cache and doubling data buffers. Given the DSP processing power and real time requirements, a complexity control scheme is implemented. A frame-level quantization scheme with quality and rate control is employed. The current implementation for video at 30 fps consumes about 90% of the chip performance at a bit rate ~2Mbps.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.