The EUV pellicle is a thin membrane intended to shield the reticle from particles. Any particles on the pellicle will be out of focus but large particles can still locally influence pattern formation. This work experimentally determines the local imaging influence dependence of particle size. A predictive model for CD change was formulated and validated. Furthermore, a linear relation between the change of CD vs. LWR was derived and found to be driven by the resist only. Therefore, the CD and LWR influence from a particle can be predicted, enabling meaningful specification limits for particle size from an imaging perspective.
Defectivity in EUV scanners gains much more importance as they move towards the high-volume manufacturing. The reticle (mask) needs to be protected from particle contamination, both inside and outside the scanner environment. One widely used method to realize this is to make use of a thin protective layer on top of the mask, which is called pellicle. In this work we investigate the impact on printed features caused by particles laying on top of the pellicle for a High-NA EUV scanner. The study was supported by simulations using the most up to date High-NA EUV scanner projected design. The most relevant lithographic metrics (namely, change in Critical Dimension, Normalized Intensity Log Slope, dose sensitivity, non-Telecentricity, Pattern Shift and Mask Error Enhancement Factor) have been considered in the study. An experimentally calibrated simulation model is used to predict the particle transmission as function of the particle size. The goal is to set a well-reasoned (based on imaging requirements) maximum particle size specification for production of pellicles and cleanliness inspection. Some sets of mask patterns and sources (use cases) that likely will be used in high volume manufacturing are considered. Furthermore, a comparison with existing 0.33 NA EUV simulation results is done.
The purpose of pellicles is to protect reticles from particle contamination, thus reducing the number of defects and increasing yield. In this paper we show how recent progress in pellicle technology has succeeded in solving the main challenges in imaging with EUV pellicles. We demonstrate this using the recent results of imaging tests in scanner, EUV reflectivity measurements, and lifetime testing. EUV light reflectivity of pellicles is one of the effects that have negatively impacted imaging with pellicles in the past. Light reflected from pellicles leads to the overexposure of neighboring fields in the corners and edges. Tests with pellicles produced using a new process show EUV reflectivity within specification of 0.04%, and measured impact on critical dimension in the corners below 0.15nm for multiple pellicles. Lifetime performance was tested by exposing up to 3000 wafers with a pellicle while periodically assessing the stability of imaging metrics. The lithometrics studies include: critical dimension (CD) and critical dimension uniformity (CDU), and contrast (via line width roughness). DoseMapper, which is an EUV scanner application developed to improve CDU, was applied during the lifetime test. Here we show that it can successfully reduce the pellicle-induced CDU and CDU over lifetime (previously shown to be dominated by pellicle EUV transmission drift). Our results using DoseMapper show that whilst intrafield CDU 3sigma increases over lifetime, it stays comfortably within the 1.1nm NXE3400 ATP specification using DoseMapper.
Vote-taking lithography is a method for mitigating mask defects, which has been applied in the 1980s to enhance yield. Vote-taking sums up N different mask images with identical content, each at 1 / N dose, to mitigate the defects on each individual mask. The fundamental assumption is that the mask defects do not correlate in position from mask to mask, and so each individual defect will be blended with good images from the other N − 1 masks. Vote-taking has recently been reconsidered for extreme ultraviolet (EUV) lithography, where it might provide a temporary solution for situations in which the defectivity conditions are not yet meeting expectations. This paper provides a thorough experimental assessment of the implementation of vote-taking and discusses its pro’s and con’s. Based on N = 4 vote-taking, we demonstrate the capability to mitigate different types of mask defects. We found additional benefits of blending different mask images, distinct from mask defect reduction. Experimental results will be shown that demonstrate improved critical dimension uniformity (CDU), both local CDU and intrafield CDU, reduced overlay errors, and smaller stochastic defect levels. Finally, we perform dedicated throughput calculations based on the qualification performance of ASML’s NXE:3400B scanner. This work must be seen in the light of an open-minded search for options to optimally enable and implement EUV lithography. Although defect-free masks and EUV pellicles are without argument essential for most of the applications, we investigate whether some applications could benefit from vote-taking.
This paper summarizes findings for an N5 equivalent M2 (pitch 32) layer patterned by means of SE EUV. Different mask tonalities and resist tonalities have been explored and a full patterning (litho plus etch) process into a BEOL stack has been developed. Resolution enhancement techniques like SRAFs insertion and retargeting have been evaluated and compared to a baseline clip just after OPC. Steps forward have been done to develop a full patterning process using SE EUV, being stochastics and variability the main items to address.
Vote-taking lithography is a method for mitigating mask defects, which has been applied in the 1980’s to enhance yield. Vote-taking sums up N different mask images with identical content, each at 1/N dose, to mitigate the defects on each individual mask. The fundamental assumption is that the mask defects do not correlate in position from mask to mask, and so each individual defect will be blended with good images from the other N-1 masks. Vote-taking has recently been brought under the attention again for consideration in EUV lithography, where it might provide a temporary solution for situations in which the defectivity conditions are not yet meeting expectations.
This paper provides a thorough experimental assessment of the implementation of vote-taking, and discusses its pro’s and con’s. Based on N=4 vote-taking, we demonstrate the capability to mitigate different types of mask defects. Additionally, we found that blending different mask images brings clear benefit to the imaging, and provide experimental confirmation of improved local CDU and intra-field CDU, reduction of stochastic failures, improved overlay, ... Finally, we perform dedicated throughput calculations based on the qualification performance of ASML’s NXE:3400B scanner.
This work must be seen in the light of an open-minded search for options to optimally enable and implement EUV lithography. While defect-free masks and EUV pellicles are without argument essential for most of the applications, we investigate whether some applications could benefit from vote-taking.
For the sub-20 nm DRAM nodes, wafer-to-wafer (W2W) variation is one of the major contributors to on-product overlay (OPO). One way to reduce the W2W variation is by applying overlay corrections on wafer level on top of per lot / per chuck corrections. These overlay corrections can e.g. be based on measurements of the OPO on the wafers to be corrected prior to rework and re-exposure. Measuring OPO on every wafer is not preferred due to the resulting metrology cost increase. Hence, wafers are typically assigned to a limited amount of groups, which are in turn assigned one common correction set for all the wafers within a particular group. The common corrections are obtained from measuring wafers from the respective groups. In this paper, we present results obtained by a different approach, where the wafer grouping is deduced from metrology data that is available prior to the exposure of the lot. Aim of this approach is to balance overlay control and OPO metrology effort. We experimentally demonstrated the benefit of our approach on one of the critical layers of a sub-20 nm DRAM product of SK hynix. The experiment was executed in a rework scenario, which involves exposing and measuring OPO on selected send-ahead (SAHD) wafers, their subsequent rework, and re-exposure of the full lot using per-group corrections derived from the OPO measurements of the SAHDs. The results of this experiment indicate a promising OPO improvement. Simulations performed on additional lots and for 3 additional layers confirm the validity of our results.
In order to optimize yield in DRAM semiconductor manufacturing for 2x nodes and beyond, the (processing induced) overlay fingerprint towards the edge of the wafer needs to be reduced. Traditionally, this is achieved by acquiring denser overlay metrology at the edge of the wafer, to feed field-by-field corrections. Although field-by-field corrections can be effective in reducing localized overlay errors, the requirement for dense metrology to determine the corrections can become a limiting factor due to a significant increase of metrology time and cost. In this study, a more cost-effective solution has been found in extending the regular correction model with an edge-specific component. This new overlay correction model can be driven by an optimized, sparser sampling especially at the wafer edge area, and also allows for a reduction of noise propagation. Lithography correction potential has been maximized, with significantly less metrology needs. Evaluations have been performed, demonstrating the benefit of edge models in terms of on-product overlay performance, as well as cell based overlay performance based on metrology-to-cell matching improvements. Performance can be increased compared to POR modeling and sampling, which can contribute to (overlay based) yield improvement. Based on advanced modeling including edge components, metrology requirements have been optimized, enabling integrated metrology which drives down overall metrology fab footprint and lithography cycle time.
As DRAM semiconductor manufacturing approaches high volume for 1x nm nodes with immersion lithography, an increased emphasis is being placed on reducing the influence of the systematic wafer-level contribution to the on-product overlay budget. The cost of the needed metrology has hitherto been challenging. However, it will be shown that the availability of fast, accurate diffraction based metrology integrated within the Lithography cluster can enable cost-effective solutions. Together with applications software we will use any relevant context information to optimize control of all exposure-tool actuators during lot processing, to deliver the needed on-product performance.
Current process corrections typically are done based on feedback per lot and per exposure chuck. Wafers exposed on the same chuck, belonging to the same lot get exactly the same process corrections. In current HVM processing however, an important contribution to the wafer variation is the differences in processing of the individual wafers. These differences can be related to variations in the usage of the processing tools (e.g. different etch chambers). An extension of the process corrections from chuck-based to process-context based can help in reducing the systematic wafer-level variation. With Integrated Metrology the sampling of wafers through the lot can be adjusted to make sure all different processing-contexts are covered in the measurements.
Finally, the impact on Litho process cycle time of the total metrology effort required to enable these performance improvements, will be evaluated, and a proposal will be made on the optimum strategy to enable high-volume manufacturing.
193nm ArF immersion microlithography has been used widely in high-volume manufacturing, and it is considered to be
the main solution below 32 nm node until extreme ultraviolet (EUV) lithography becomes ready. Laser systems are now
enlarging its function and capability to meet various applications. In this paper we report a newly developed solution for
focus drilling technique applied to increase the depth of focus (DoF) for patterning contacts, vias and trenches. The laser
light is stabilized at any E95 in the range from 0.3 pm to 2.5 pm, where E95 is defined as the width of the spectral range
that contains 95% of the integrated spectral intensity. The high-range bandwidth is realized by introducing a newly
developed line narrowing module (LNM) in the oscillator resonator. The bandwidth is measured with the on-board
Fabry-Perot etalon and well controlled. This technique is easy upgradable to Gigaphoton latest GT62A-1SxE with the
flexible output power (60W - 90W) and stabilized spectrum (E95=0.3pm). In comparison to another focus drilling
technique where the large DoF is achieved by tilting a wafer stage during scan, the increase of the bandwidth of light
source has much smaller impact on the required performance of the scanner such as productivity, overlay and critical
dimension uniformity (CDU). In the paper we present the data that indicate the increases in DoF with broadening of the
laser spectrum as well as imaging and overlay results obtained at high bandwidth.
In this paper we discuss a laser focus drilling technique which has recently been developed for advanced
immersion lithography scanners to increase the depth of focus and therefore reduce process variability of contact-hole
patterns. Focus drilling is enabled by operating the lithography light-source at an increased spectral bandwidth, and has
been made possible by new actuators, metrology and control in advanced dual-chamber light-sources. We report wafer
experimental and simulation results, which demonstrate a process window enhancement for targeted device patterns.
The depth of focus can be increased by 50% or more in certain cases with only a modest reduction in exposure latitude,
or contrast, at best focus. Given this tradeoff, the optimum laser focus drilling setting needs to be carefully selected to
achieve the target depth of focus gain at an acceptable contrast, mask error factor and optical proximity behavior over
the range of critical patterning geometries. In this paper, we also discuss metrology and control requirements for the
light-source spectrum in focus drilling mode required for stable imaging and report initial trend monitoring results over
several weeks on a production exposure tool. We additionally simulate the effects of higher-order chromatic aberration
and show that cross-field and pattern-dependent image placement and critical dimension variation are minimally
impacted for a range of focus drilling laser spectra. Finally, we demonstrate the practical process window benefits and
tradeoffs required to select the target focus drilling laser bandwidth set-point and increase effectiveness of the sourcemask
solution for contact patterning.
The laser bandwidth and the wavelength stability are among the important factors contributing to the CD Uniformity
budget for a 45 nm and 32nm technology node NV Memory. Longitudinal chromatic aberrations are also minimized by
lens designers to reduce the contrast loss among different patterns. In this work, the residual effect of laser bandwidth
and wavelength stability are investigated and quantified for a critical DOF layer. Besides the typical CD implications we
evaluate the "image placement error" (IPE) affecting specific asymmetric patterns in the device layout. We show that
the IPE of asymmetric device patterns can be sensitive to laser bandwidth, potentially resulting in nanometer-level errors
in overlay. These effects are compared to the relative impact of other parameters that define the contrast of the
lithography image for the 45nm node. We extend the discussion of the contributions to IPE and their relative importance
in the 32 nm double-patterning overlay budget.
Cost of ownership of scanners for the manufacturing of front end layers is becoming increasingly expensive. The ability
to quickly switch the production of a layer to another scanner in case it is down is important. This paper presents a
method to match the scanner grids in the most optimal manner so that use of front end scanners in effect becomes
interchangeable. A breakdown of the various components of overlay is given and we discuss methods to optimize the
matching strategy in the fab. A concern here is how to separate the scanner and process induced effects. We look at the
relative contributions of intrafield and interfield errors caused by the scanner and the process. Experimental results of a
method to control the scanner grid are presented and discussed. We compare the overlay results before and after
optimizing the scanner grids and show that the matching penalty is reduced by 20%. We conclude with some thoughts
on the need to correct the remaining matching errors.
Overlay requirements for DRAM devices are decreasing faster than anticipated. With current methods overlay becomes
ever harder to control and therefore novel techniques are needed. This paper will present an alignment based method to
address this issue. The use and impact of several non-linear alignment models will be presented. Issues here include the
number of alignment marks to use and how to distribute them over the wafer in order to minimize the throughput impact
while at the same time providing maximum wafer coverage. Integrating this method into a R2R environment strongly
depends on the stability of the process. Advantages and disadvantages of the method will be presented as well as
experimental results. Finally some comments will be given on the need and feasibility of wafer by wafer corrections.
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