For the past few decades, PPA (performance, power, and area) demand of computation infrastructure has been driving exponential increase of chip density. In recent years, the challenges of printability and process window for advanced manufacturing node continuously motivated innovations in reticle enhancement techniques, notably the adoption of inverse lithography technology (ILT) and curvilinear mask. We have observed a few challenges: 1) ILT provides unmatched quality of results but does incur additional computation time to manage; 2) for curvilinear mask, though the benefits are evident, the associated data volume is very large; and 3) mask consistency remains a critical component for design manufacturability. To utilize the advanced RET techniques to their full potential, it is crucial to identify the repeating structures in design layout and reuse the correction result, getting three benefits at the same time: reducing mask preparation runtime, reducing mask data volume, and improving mask consistency. Conventional layout repetition analysis is based on native design hierarchy. However, in many cases, the input layout for mask synthesis flows is either completely stripped of hierarchy or contains sub-optimal hierarchy. Some layout hierarchy can be detected and reconstructed using manual methods such as using user generated pattern library of highly repeating structures in conjunction with pattern matching technology. However, the preparation of such libraries is a formidable effort, and a significant number of repetitions in designs will be overlooked by this approach. In this paper, we investigate the automatic detection of repeating geometry structures and formed a hierarchy that is optimized for mask synthesis. The detection supports any process layer and both Manhattan and all-angle designs. The engine detects repeating regions of arbitrary shape. The detected repeating structures can also be applied within the chip or across chips to accelerate correction to further improve mask consistency. By scaling well to hundreds of processors, the distributed hierarchy extraction is very efficient for a full chip layout. For highly repetitive layouts, mask synthesis runtime reduction of more than an order of magnitude has been observed by performing this hierarchy extraction.
As feature sizes and pitches continue to decrease, more complex correction algorithms are needed to solve increasingly difficult geometric configurations. Usage of these more complex algorithms results in unacceptably long time-to-mask when applied to an entire design. In many cases, the more complex algorithms are only required in a small percentage of areas of the entire design, and these areas are not always known prior to tapeout. Hotspot fixing (HSF) flows are increasingly used to fix these hotspot areas to minimize errors and decrease time-to-mask. These flows involve “recorrecting” a design, using the previous correction output as the input to the HSF flow. This input file contains a hierarchy that was optimized for the original correction. Hotspot areas are frequently smaller than the original correction areas and frequently repeat in unique cell outputs of the original correction, so the optimal hierarchy for a HSF fix flow may be very different from the original correction. A new hierarchy, optimized for HSF, is difficult to form from the corrected output. This paper describes the usage of pattern-matching to regain hierarchical compression for identical hotspot areas that are not repeating cells in the original correction. Using this pattern-matching HSF flow, turnaround time for the hotspot fixing can be more than 50X faster than re-using the original correction’s hierarchy for complex HSF methods. These significant gains can be achieved in spite of the additional complexity it can add to the flow. In the case where simpler/faster HSF correction methods are used, significant turnaround time gains can still be made by using this pattern matching technique.
Hotspot fixing methodologies are increasingly deployed during tapeouts as a means to optimize the tradeoffs between complex, highly accurate correction methods and faster methods that are sufficient for most pattern areas.1 However, pattern database hierarchies may not be optimum for these hotspot fixing flows, as they are optimized for the initial correction run or method. This paper examines the usage of pattern matching to regain hierarchy and significantly reduce turn-around-time for complex hotspot fixing methods. Gains in turn-around-time can be well over 50 times faster than reusing the original correction’s hierarchy.
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