The stimulated Raman amplification of picosecond Stokes pulse is numerically investigated in ultra-small
silicon-on-insulator optical waveguide. Numerical results show that we obtain the gain of up to 30-dB for weak Stokes
pulse in the co-propagation configuration for 10-mm-longth waveguide using high intensity pump optical pulse. The
peak gain, pulse width, rise time, and fall time of Stokes pulse will experience the variation course of decaying then
increasing with increasing waveguide length. The time delay of output Stokes pulse is controlled by adjusting the initial
time delay of both pump and Stokes pulses.
The configuration of polymer light waveguide electro-optical printed circuit board(EOPCB) is proposed in this paper. An
additional optical layer with light waveguide structure is used in conventional PCB to construct EOPCB. Light
waveguide core layer mould is made with SU-8 photolithograph. Polymer light waveguide layer which is embedded
between multiplayer PCB is made in experiment by Doctor-blading technology for large size application. Vertical cavity
surface emitting laser (VCSEL) array is used as optical transmitter array. PIN photodiode array is used as optical
receiver array. A MT-compatible direct coupling method is presented to couple light beam between optical
transmitter/receiver with light waveguide layer. The optical signals from a processor element chip on the PCB can
transmit to another processor element chip on the same PCB board through light waveguide interconnection in EOPCB.
So optical interconnection between chip to chip for parallel multiprocessor system can be reailzed by EOPCB.
A three-dimensional (3-D) 4×4×4 optical interconnect Mesh network scheme for parallel multiprocessor system based
on polymer light waveguide electro-optical printed circuit board(EOPCB) is proposed in this paper. The Mesh
topological structures of light waveguide interconnects for processor element chip-to-chip on a board, and board-toboard
on backplane is constructed. The system consists of 64 processor element chips interconnected in a 3-D Mesh
network configuration. Every processor board comprises 4x4 processor element chips with Mesh interconnection.
Board-to-board Mesh interconnects are established on a backplane through light waveguide Mesh interconnect
topological structure. An additional optical layer with light waveguide structure is used in conventional PCB to construct
EOPCB. Vertical cavity surface emitting laser (VCSEL) array is used as optical transmitter array. PIN photodiode array
is used as optical receiver array. A MT-compatible direct coupling method is presented to couple light beam between
optical transmitter/receiver with light waveguide layer. The optical signals from a processor element chip on a board can
transmit to another processor element chip on another board through light waveguide interconnection in the backplane.
So 3-D optical interconnection Mesh network for parallel multiprocessor system can be reailzed by EOPCB.
A novel Mesh optical interconnection board configuration in free-space is considered in this paper. Based on Mesh optical interconnection topology principle, this design is specially designed for integrated chip interconnection on high performance occasion as tiny satellites. The system uses VCSELs as electronic-to-optics converter modules to implement conversion between electronic signals and optical ones. Then optical signals, which have better anti-interference than electronic signals, propagate in free-space in a robust way. And at the interconnected chip side, which could only process electronic signals, optical signals are needed to be converted by PIN arrays into electronic ones. All interconnections are skillfully finished by certain cube prisms and inclined 45o reflecting mirrors and limited on the optical-waveguide layer inserted in a PCB board. This paper emphasizes on the configuration of an interconnecting unit (considered as a processing element) and its connecting manner. The design aims at light-weight, small-bulk, great anti-interference, advantages at better robustness, lager throughput, especially suitable for data switch, data propagation and IC interconnection on the tiny satellite.
Greedy demand of high speed communication has made electrical interconnection on board a bottleneck. Electro-Optical Printed Circuit Board (EOPCB) was proposed to relieve the pressure by introducing an optical layer to common printed circuit board. Nowadays, most of the proposed EOPCB solutions focused on the design of optical transceiver structure and optical interconnection was used directly to replace high speed electrical interconnection by employing transceiver arrays. This approach would need many VCSEL-PIN pairs for a single high speed chip on board, thus increase the cost and also decrease the efficiency of optical interconnection. To defeat the weakness, a network approach, where only one VCSEL-PIN pair is required for a chip, is proposed in this paper. A novel Optoelectronic
integrated circuit (OEIC) architecture is introduced to make this network approach possible.
Currently the mainstream technology of SAN is SAN storage virtualization and its implementation. The switch-based storage virtualization embeds the virtualizer in the core of the storage networking fabric in an "intelligent switch" rather than an appliance or a host. This paper describes the SV-FC SAN switch's hardware and software architecture. The main aid of design and implementation the switch is to give a new way to realize FC-SAN storage virtualization. Storage virtualization modules are embedded in the switches firmware. The switch can provide simple and friendly interfaces for users to configure and manage the FC SAN.
A wavelength 0.85μm-based optical power splitter designed with Multi Mode Interference (MMI) by ion exchange on K9 glass was introduced. The waveguide material is K9 glass made in China and formed by K+-Na+ pure melt salt ion exchange method. The grade index profile of planar ion-exchanged waveguide on K9 was studied and accorded with erfc function through compare of experimental and theoretic index profiles. The fabrication process of planar ionexchanged waveguide device was described. The basic theory of 1×8 MMI optical power splitter was illuminated by using guided-model propagation analysis. The working wavelength is 0.85μm, and the structure parameters of 1×8 MMI splitter were designed. The core pitch on this chip is chosen as 250μm to take the fiber connections into account, and the typical cladding diameter of optical fibers as 125μm. The critical parameters in the fabrication of the MMI power splitter are the multimode section width and length. In general the key performance specifications of the optical power splitter are insertion loss and uniformity. The output performances and the refractive index change's influence of the device were simulated by Bear Propagation Method (BPM). The uniformity was 0.93×10-2dB, the average insertion loss was 9.12dB, and the maximal insertion loss was 9.14dB. The result shows that the advantages of the method include low loss, ease of fabrication, and low material cost.
This paper proposes a novel 4×4 free-space bi-directional fiber optical switch. The switch is independent of the optical polarization, which can lead to polarization-dependent loss. When the input light beam incident on the polarization beam splitters (PBS) coating satisfies Brewster Condition, it is decomposed into two orthogonal linear polarized lights: P-polarized light and S-polarized light. In the paper, the free-space optical switches elements include a polarization control unit and a routing unit, and the former will be discussed emphatically. The polarization control unit can be acted by Ferroelectric Liquid Crystal (FLC) or half-wave plate array. By comparing the two methods, half-wave plate array will be chosen in the experiment. The controlling circuit of driving half-wave plate array is designed and polarization-dependent loss (PDL) in 4×4 optical switch using half-wave plate array is analyzed. The experiment results indicate that the insertion loss is less than 4.4 dB, the interchannel crosstalk is about 32 dB and the switching time of the optical switch is about 2 ms.
RRP has two means to transmit data: store-and-forward and cut-through. In this paper, the high and low priority packet transfer delay of the N nodes Resilient Packet Rings (RPR) in store-and-forward architecture is analyzed based on the queuing theory. According to queuing theory, we set up the nodes model and analyzed the factors that influenced the packet transfer delay in a constrained condition. By calculation and simulation, the result indicates that both high priority and low priority packets’ delay increase with the node number N of the RPR rings. The high priority traffic has less packet delay than the low priority traffic at the same node number N. The increase of the low priority transfer delay is much larger than the high priority traffic with the increase of the node number.
In the parallel processing system, large numbers of processors are interconnected in order to improve the performance of the computer, such as the symmetric multiprocessor (SMP) architecture. When the basic node is an SMP or a computer having a single processor, the characteristics of an interconnection networks are important factors which influence the performance of the entire system. Fibre Channel (FC) has a lot advantages, such as excellent scalability; the bandwidth is large; delay time is short and fault tolerance is large. It is assumed that an SMP is used for a basic node. We construct the cluster system using FC as interconnection network, which are a fabric method and a FC Arbitrated Loop (FC-AL) method. According the method, if the number of nodes supported by the interconnection network is small, the addition of extra nodes can be added at small expense. The bandwidth of each node is large, the delay time is short, and the fault tolerance effect is large in the interconnection network. In the case of connecting to a shared disk, a large bandwidth is provided and time required for gaining access to the shared disk becomes short.
In order to find the optimal design for a given specification of an optical communication link, an integrated simulation of electronic, optoelectronic, and optical components of a complete system is required. It is very important to be able to simulate at both system level and detailed model level. This kind of model is feasible due to the high potential of Verilog-AMS language. In this paper, we propose an effective top-down design methodology and employ it in the development of a complete VCSEL-based optical links simulation. The principle of top-down methodology is that the development would proceed from the system to device level. To design a hierarchical model for VCSEL based optical links, the design framework is organized in three levels of hierarchy. The models are developed, and implemented in Verilog-AMS. Therefore, the model parameters are fitted to measured data. A sample transient simulation demonstrates the functioning of our implementation. Suggestions for future directions in top-down methodology used for optoelectronic systems technology are also presented.
A chip-to-chip optical interconnection solution on PCB is presented in this paper. Both electrical and optical interconnections are used in common printed circuit board (PCB) to construct electro/optical PCB (EOPCB). An additional optical layer with waveguide structure is used in the PCB. So the EOPCB integrates the information medium "light" into the board. Optical transmitter is vertical cavity surface emitting laser (VCSEL) array. Optical receiver is PIN array. VCSEL array with its driver IC chip and PIN with its receiver IC chip are bonded with LSI chip by ball-grid array (BGA) technology. Then the LSI chips with VCSEL and PIN arrays are bonded on PCB by surface-mount technology (SMT). Multimode waveguides are used as optical layer in PCB. In order to couple light beam between optical transmitter/receiver with waveguide layer, a direct coupling method by the waveguide with 45° end face is presented. VCSEL chip is placed close to the 45° end face of the waveguide. The light beams from VCSEL array are emitted into the 45° end face directly and reflected by 90°, then coupled into the waveguide layer. No microlens arrays are needed for collimating light beam array in this configuration. A proof-of-principle experiment is made to verify the feasibility of this approach.
This paper presented a silica-based 1×8 optical power splitter at 0.85μm designed with Multi Mode Interference (MMI). The waveguide material is Si-based SiO2 doped with Ge and deposited by PECVD (Plasma Enhanced Chemical Vapor Deposition) method. The refractive index of glass substrate is 1.458, and the index difference is 0.75%. The input and output waveguides are optimized considering the characteristics of VCSEL (Vertical Cavity Surface Emitting Lasers). The core pitch on this chip is chosen as 250μm to take the fiber connections into account, and the typical cladding diameter of optical fibers as 125µm. The critical parameters in the fabrication of the MMI power splitter are the multimode section width and length. In general the key performance specifications of the optical power splitter are insertion loss and uniformity. We use a Finite Difference Beam Propagation Method (FDBPM) to simulate accurately the evolution of the fundamental mode power of the input guide incoming to the device, and analyze the relationships of various parameters in detail. The bend output waveguides are sin-bend styles. Compared with the commercial optical power splitter, the simulation results accord with the requirement of our design, containing compact size, low loss, stable splitting ratio, low crosstalk, large optical bandwidth, and good fabrication tolerances. The insertion loss and the uniformity of pilot study are 9.07dB and 0.02dB respectively.
The problem of ion-exchanged waveguides that the waveguides burial-depth strongly depends on waveguide width was investigated in this paper. We resolved this problem by using a special ion-exchanged waveguides fabrication technique and wavelength multiplexers based on the array-waveguide grating (AWG) principle are fabricated with ion-exchanged waveguides in glass for 1550nm. The process of the waveguides fabrication and the devices propagation characteristics are presented. The insertion loss is below 8.5dB and with a cross talk of -20dB for 16-channel 100GHz devices benefit from the burial-depth uniformity between channel waveguides and slab waveguides. The AWGs are almost polarization insensitive because the refractive index profile of the waveguides is nearly concentric and the waveguides are diffused into stress-free glass substrates, same as the waveguides material approximately. The transverse electric / transverse magnetic (TE/TM) shift of the wavelength response is only 0.03nm for a 16-channel 100GHz AWG.
This paper reported an improved optical switching network configuration based on optical interconnection technology with vertical cavity surface emitting laser (VCSEL) array. The optical switching network consists of two-level optical interconnection backplane. It can connect 64 nodes with parallel optical links. The first level of optical interconnection backplane includes eight 8×8 crossbar interconnect sub-networks. Instead of one 8×8 crossbar interconnect sub-network in the second level of the optical interconnection backplane adopted in our original configuration, the second level of optical interconnection backplane has two 8×8 Crossbar interconnect sub-networks in this improved configuration. So the blocking rate is decreased. VCSEL-based parallel optoelectronic I/O interface is used as O/E conversion. Every I/O parallel interface between optical interconnection network and every node includes 18 VCSEL emitter pixels, 18 PIN receiver pixels. In order to couple 18 signal light beam array into optical fiber array ribbon, a fabrication technique based on the high precise position slot is used for assembling optical fiber array interface. A configuration of coupling packaging for the VCSEL pixel array to the fiber array with 45° end surface is also presented in this paper. An optical data transmission rate between interconnection nodes is 5Gb/s which is transmitted by the optical fiber ribbon-based parallel optical data links with 2 channels at data rate of 2.5Gb/s per channel. The aggregate bandwidth of 360Gbps for an 8×8 Crossbar optical fiber interconnect network backplane is achieved. The reliability of the fiber array with 45° end surface is tested in our experiment.
This paper describes the design of an OIF-approved 10Gbps very short reach parallel optical interconnect demonstrated system. It is a 12x1.25Gb/s channel parallel optics solution, leveraging the low cost transceiver (850nm VCSEL), and CMOS (SERDES) technologies originally developed for Gigabit Ethernet. The demonstrator comprises of SONET/SDH serial OC-192 interface, CPLD based convert IC, 1.25Gbps 12-channel parallel optical transmitter and receiver. The transmitter includes a 12-channel array of 850nm VCSEL, a 12-channel VCSEL driver LSI, and a precise coupling structure for 12 multi-mode-fibers ribbon. The receiver consists of a 12-channel array of pin-PDs, a 12-channel receiver LSI, and a precise coupling structure for 12 multi-mode-fibers ribbon. A CPLD chip, which maps the OC-192 framer onto the parallel optical links, and reassembles it after detection, has been developed. We also present the coupling package configuration for VCSEL arrays to fiber ribbon.
A 5 to 10 Gbps bandwidth optical interconnecting and switching network system used on parallel computing is introduced in this paper. This system provides a high bandwidth to meet the request of high bandwidth of the parallel computing. Optics is used to be a media to carry data and optical crossbar interconnection board is used to switch data in this system. It comes over the inherent disadvantage of the R, L, C delay and clock skew of the electronics interconnection. This system has good stability and scalability.
A novel hybrid electrical optical Clos switch network for multiprocessor cluster system was presented. For multiprocessor cluster system of 128 hosts, the novel optical Clos network includes 16 basic modules, a passive optical fiber backplane with (8×15)×16 which has a total of 1920 optical data channels and a signaling control system. The basic module is composed of the input line cards of 8 hosts, a single chip of 16×16 crossbar switch, parallel transmitting VCSEL modules for fan-out of (16-1)optical fiber channels and (16-1)×1 optical combiners. The passive optical fiber backplane of very large capacity and high density, based on linear VCSEL arrays and fiber ribbon technology, is to be used to interconnect between hosts of different sub-clusters. The routing of the optical Clos switch network is decided by a signaling control system. Compared with high performance electronic system, this technology offers a relatively easy and simple means of communicating large amount of information between hosts, and lower delay time.
A novel photonic switching network with vertical cavity surface emitting laser (VCSEL) array packaging for parallel multiprocessor cluster system is described. The parallel multiprocessor cluster system provides 64 serve nodes connected by photonic switching network with parallel optical links. There are eight cluster subsystems in the system. Each subsystem includes eight computing nodes and an optical interconnect backplane of 8x8 crossbar optical interconnection network with VCSEL-based optoelectronic I/O parallel interface. Every I/O parallel interface between optical interconnection network and every computing node includes 16 VCSEL emitter pixels, 16 PIN receiver pixels. In order to couple 16 signal light beam array into optical fiber array ribbon, a fabrication technique based on the high precise position slot is used for assembling optical fiber array interface. A packaging structure for optical fiber array interface is presented. As the position slots of optical fiber array interface are formed by VLSI photolithography and IcP etch techniques, and etching depth is smaller compared with V-groove slot, the high precision slots with 25Ojtm pitch can be obtained. A configuration of coupling packaging for 16 VCSEL pixel array to 16 fiber array with 45° end surface is also presented in this paper.
A photonic switching network for parallel multiprocessor cluster system using vertical cavity surface emitting laser (VCSEL) arrays is described. The parallel multiprocessor cluster system provides 64 server nodes interconnected by optical interconnection network with parallel optical links. There are 8 cluster subsystems in the system. Each subsystem includes 8 computers and an optical interconnect backplane of 8x8 crossbar optical interconnection network with VCSEL-based optoelectronic I/O interface. An optical data transmission rate between computers is 5Gb/s which is transmifted by the optical fiber ribbon-based parallel optical data links with 2 channels at data rate of 2.5Gb/s per channel. Every I/O interface between optical interconnection network with each computer includes 16 VCSEL emitter pixels, 16 PIN receiver pixels. VCSEL emitter pixels transformed electrical signals from PCI bus of computer into optical signals, where PIN receiver pixels transformed optical signals from optical interconnect network backplane into electrical signals. The whole optical interconnection network is composed of two level optical interconnect backplanes. A total of 64 computers propagating for data communication of 8 subsystems would be realized.
A novel 2 X 2 free-space polarization-independent bi-directional fiber optical switch is presented in this paper. A general formula for coupling-loss of fiber collimators is derived. The insertion loss and crosstalk are analyzed in detail. The experiment results indicated that the insertion loss was less than 1. 1 dB, the interchannel crosstalk was about 18.5 dB, and the switching time was about ims. The new kind of configuration of the optical switch grants the features of few optical components, high compactness, low optical interchannel crosstalk, fast switching speed, polarization insensitivity, and easiness of optical assembly.
An optical interconnection network with parallel optical links for multiprocessor cluster system of 256 nodes is described. There are 16 subsystems in the system, in which each subsystem includes 16 computers and an optical fiver-ribbon interconnection plate of 16X16 crossbar interconnection network with VCSEL-based opto-electronic
interface. An optical data rate between computers is 5Gb/s which is transmitted by the optical fiber-ribbon based parallel optical data links with 4 channels at data rates of 1.25Gb/s per channel. Every interface between optical interconnection network and each computer includes 16X4 VCSEL pixels, 16X4 PIN pixels and (1X16)X4 electrical
switch. The whole optical interconnection network is composed of two level optical networks. There are sixteen optical fiber-ribbon interconnection plates of 16X16 crossbar interconnection network in the bottom level. The top level optical interconnection network would be an optical fiber-ribbon interconnection plate with a total of
2084 data channels propagating for communication of 16 subsystems.
This paper presents a novel 4 X 4 free-space polarization- independent bidirectional fiber optical switch based on 2 X 2 optical switch module. The optical architecture of the 4 X 4 optical switch is designed. The routing path for different switching state is analyzed in details. The performance analysis for this 4 X 4 fiber optical switch architecture is derived. The insertion loss of the 4 X 4 optical switch architecture is less than 4.4 dB and the interchannel crosstalk is less than -74 dB. The switch time is in microsecond range. This new kind of architecture of the optical switch grants the features of less optical components, high compactness, low optical interchannel crosstalk, fast switching sped, polarization insensitivity and easiness to optical assembly.
In this paper, a kind of free-space optical switch based on polarization was proposed. Its operation principle was described in detail. Based on this method, some basic types of optical switches were presented, such as 1 X 2, 2 X 1 and 2 X 2 optical switches. Then, taken as an example, the 1 X 2 type was tested to give the experiment performance of this kind of free-space optical switch based on polarization. Its insertion loss was less than 3 dB, crosstalk between different channels were as low as -32 dB, and its switching time was about 2 ms. It showed that this kind of optical switches could be well used in OADM for optical networks protection and reconfigurration. Also its disadvantages were discussed at the end of this paper.
This paper proposes a novel optical crossbar switching architecture. The proposed IP switch is based on an optical crossbar switching system, which take full use of advantages of electronics and photonics to face the challenge of the terabits per second IP switching. Group interconnect network is regarded as an ideal switching structure for its low blocking and excellent scalability. We add feedback loops to the group interconnect network, and got the better performance at the cost of slight extra hardware. In the paper, we simulated the cell loss rate of our optical crossbar switching network with feedback loops and several other switching network in the condition of uniform traffic and the burst traffic. The result shows that, in uniform traffic, the cell loss ratio (CLR) of our novel structure is less than 10e-9 , which is much lower than others; while in burst traffic, the CLR of ours is also lower than any of others. The hardware implementation of the switching network is also discussed. We proposed a high density optical waveguide interconnect board based on VCSEL/MSM detector arrays and free-space optical interface modules, which grants the features of high density signal channel, low cell loss rate, low optical interchannel crosstalk, small volume and simple structure.
This paper presents a novel multibuffer-shared ATM switching architecture based on optical interconnects and optoelectronic hybrid crossbar modules. The core of this switching architecture is the 16 X 16 CMOS-SEED crossbar switching module, and the optical interconnects between the input interface and switching core provide high-speed data paths. Many buffers placed in an output module of the interface are partial shared, which take advantages of output buffer and shared buffer, so these buffers are used more effectively than the output buffer. And these shared buffers bring an advantage that the speed of the accessing each of these buffers is not need very high due to these buffers can write/read many cells in a parallel way. The performance of this ATM switching system is analyzed under the uniform traffic and bursty traffic. The simulation results show that the cell loss probability of this ATM switching system is less than 10e-9 under the uniform traffic with 12-cell length of each shared- buffer, and the cell loss probability is less than 10e-9 under the bursty traffic with 160-cell length of each shared-buffer.
A novel optical implementation method of 4 X 4 polarization-independent bi-directional fiber optical switch in free-space optical architecture is presented in this paper. This 4 X 4 fiber optical switch is based on elementary 2 X 2 optical switch module. The 4 X 4 optical switch constituted by polarization beam splitters (PBS), 1/4 waveplates (QWP), polarization light modulator (PLM), right angle prism (RAP), and total reflection mirror (TR). Operation is independent by input signals of polarization of the optical beams. This new kind of configuration of the optical switch grants the features of less optical components, high compactness, low optical interchannel crosstalk, fast switching speed, polari insensitivity, and easiness to optical assembly. A matrix description is deduced with respect to this 4 X 4 fiber optical switch architecture.
IP traffic on the Internet and enterprise networks has been growing exponentially in the last several years, and much attention is being focused on the use of IP multicast for real-time multimedia applications. The current soft and general-purpose CPU-based routers face great stress since they have great latency and low forwarding speeds. Based on the ASICs, layer 2 switching provides high-speed packet forwarding. Integrating high-speed of Layer 2 switching with the flexibility of Layer 3 routing, Layer 3 switching (IP switching) has been put forward in order to avoid the performance bottleneck associated with Layer 3 forwarding. In this paper, we present a prototype system of a scalable IP switching based on scalable ATM switching fabric and optical interconnect. The IP switching system mainly consists of the input/output interface unit, scalable ATM switching fabric and IP control component. Optical interconnects between the input fan-out stage and the interconnect stage, also the interconnect stage and the output concentration stage provide high-speed data paths. And the interconnect stage is composed of 16 X 16 CMOS-SEED ATM switching modules. With 64 ports of OC-12 interface, the maximum throughput of the prototype system is about 20 million packets per second (MPPS) for 256 bytes average packet length, and the packet loss ratio is less than 10e-9. Benefiting from the scalable architecture and the optical interconnect, this IP switching system can easily scale to very large network size.
In this paper, the crosstalk influence between signal channels of 4 X 48 free-space parallel optical interconnect network system based on VCSEL/CMOS optoelectronic chip and 2-D optical fiber data link is studied. The crosstalk analysis shows that the crosstalk between signal channels may be reduced by introducing a small displacement at vertical direction. This optical interconnection system can realize 12-bit wide bi- directional data transfer between four computers through a 4 X 48 high density 2-D optical fiber data link. The influence of the crosstalk would be reduced in this optical interconnect system.
A 4 X 4 optical switch performing bi-directional crossbar switching on optical communication signals at 1550 nm is presented and experimented. This switch is expanded from several elementary 1 X 2 optical switches. The switch is made of bulk passive components. Operation is totally polarization independent. The proposed free-space architecture has the features of high compactness, reliability and fast response time compared with common switching solutions.
A new free-space multistage optical interconnection network which is called the Comega interconnection network is presented. It has the same topological construction for the cascade stages of the Comega interconnection. The concept of the left Comega and the right Comega interconnection networks are given to describe the whole Comega interconnection network. The matrix theory for the Comega interconnection network is presented. The route controlling of the Comega interconnection network is decided based on the matrix analysis. The node switching states in cascade stages of the 8 by 8 Comega interconnection network for the route selection are given. The data communications between arbitrary input channel with arbitrary output channel can be performed easily.
KEYWORDS: Switching, Asynchronous transfer mode, Optical interconnects, Solar concentrators, Interfaces, Computer simulations, Optoelectronics, Electronic components, Signal processing, Free space optics
A growable multistage ATM switching architecture based on optical interconnect is presented in this paper. The interconnect stage, core of the 3 stages architecture, is composed of 16 by 16 CMOS-SEED optoelectronical hybrid ATM switching modules. Since the interconnect stage is memory- less, electronic buffers are provided in the output concentrator stage, and the buffers are partial shared to be used effectively. Optical interconnects between the pair- input expansion stage and the interconnect stage, also the interconnect stage and the output concentrator stage provide high-speed data paths, for example 622Mb/s or 2.4 Gb/s. Both the with lower speed control signal and the complicated logical processing are carried out in the electronic devices. With 64 ports of OC-12 interface, the maximum throughput of the prototype system is about 40 gigabits per second, an the packet loss ratio of this ATM switching system is less than 10e-9. Taking advantages of high speed of the optical interconnect and the high density, flexible logical processing of the electronic devices, the ATM switching of the optical interconnect and the high density, flexible logical processing of the electronic devices, the ATM switching system has favorable potential to scale easily to very large network size, for example 256 ports of OC-48 interface.
An optoelectronic switching network with 2-D optical fiber bundle arrays I/O access device is presented in this paper. An optoelectronic recirculating Banyan network based on CMOS/SEED smart pixel device is used in this configuration. Thirty-two X two single-mode fiber bundle array and 32 X 2 multi- mode fiber bundle array are fabricated respectively based on the features of high density, high precision and array permutation of the CMOS/SEED optoelectronic integrated devices. The measuring results show that the center to center spacing between adjacent optical fibers in the same layer of the fiber array is 125 micrometer, and the spacing between adjacent layers is 500 micrometer. Displacing tolerance of the fiber bundle arrays is less than 2 micrometer and the angular tilt error is less than 0.02 degree.
A 16 X 16 Crossover photonic switching network with hybrid integrated CMOS/SEED smart pixel device and 2D optical fiber bundle array I/O access device is reported in this paper. SEEd array devices ar used as light receivers and transmitters, while CMOS devices make efficient logical processing. 4 X 40 2D multilayer optical fiber bundle arrays are fabricated and are used as I/O access devices in the crossover photonic switching network. The center to center spacing between adjacent optical fibers in the same layer of the fiber array is 125micrometers , and the spacing between adjacent layers is 250micrometers . Displacing tolerance of the fiber bundle arrays is less than 4 micrometers and the angular tilt error is less than 0.03 degree. It has the feature of high density, high precision, array permutation and easy to couple with 2D CMOS/SEED smart pixel device.
In this paper, a novel optoelectronic sorting network with recirculating architecture is presented. It can realize fast sorting with large number of data in low spatial complexity. This is achieved by using parallel optical interconnect (implemented by a 1 X 2 binary phase grating), introducing a recirculating architecture, and using the array of Compare- and-Exchange (C&E) implemented by CMOS-SEED hybrid integrated circuit.
Self-electrooptic effect devices (SEEDs) and GaAs field- effect transistors (FETs) are used to form smart pixels. A 8 X 4 array of simple field-effect transistor-self- electrooptic effect device (FET-SEED) smart pixels has been fabricated by interconnecting a SEED chip and a GaAs FET chip on a printed circuit board. The smart pixel consists of a detector SEED, a modulator SEED, and a simple GaAs FET amplifier. An optical system have been designed and constructed to demonstrate the smart pixels. The operational principle of the smart pixels is also described.
The design theory of fresnel microlens is described and the errors introduced by fabricating process are analyzed. The fresnel microlens arrays of four-level phase with diffractive efficiency larger than 60% are obtained. Crossover optical interconnect module is constructed by using fresnel microlens arrays.
Optical interconnection networks have potential uses in parallel processing computers and photonic switching systems. This paper presents the topology of nonblocking omega network (NON) and studies the topological equivalence variety of NON with Benes network by the graph analysis method.
A general algorithm, the graph analysis method (GAM), to determine the topological equivalence of interconnection networks (INs) is presented. The concept of topological equivalence variety of INs is introduced. Topological equivalence variety of crossover networks with omega and banyan networks are studied by the GAM.
This paper presents a new optoelectronic hybrid numerical system for the parallel processing of algebra polynomial evaluation. Free-space optical perfect shuffle interconnection network is adopted in our systems. Optical interconnection networks can make the operating time the minimum, which is proportional to log2N.
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