In this paper, a phase retrieval method using the Hilbert transform (HT) and low-rank method is proposed to obtain differential phase contrast (DPC) imaging. The method has the following advantages: 1. A single grating system can be implemented without the mechanical movement of the grating. 2. The complex computation of the phase retrieval method by the fast Fourier transform (FFT) method can be avoided. 3. The noise rejection by the low-rank can be handled due to fringes from the various energy bins. Specifically, the low-rank method is the singular value decomposition (SVD) by the rank-one property. The phase retrieval of the HT method and noise filtering by the lowrank method have been performed to validate the proposed method. The proposed method provided the clear boundary division between the sample area and the air area. The boundary division of the high energy image between the sample area and the air area was improved with the low rank method (resulting in a sharp division). Moreover, the profile of the DPC image obtained by HT had symmetrical form similar to the theoretical profile.
We present preliminary experimental results of X-ray phase-contrast imaging with a tilted-grid to measure the twodimensional phase gradient. The direction of the grid line is rotated 10 degrees relative to the horizontal axis. To obtain the differential phase-contrast image, we employ the spatial harmonic method based on the Fourier transform phase retrieval. The two-dimensional phase gradient of a PMMA sample is well defined in the phase-contrast image acquired with the tilted-grid setup.
We present new scheme for chip-level photonic I/Os, based on monolithically integrated vertical photonic devices on bulk silicon, which increases the integration level of PICs to a complete photonic transceiver (TRx) including chip-level light source. A prototype of the single-chip photonic TRx based on a bulk silicon substrate demonstrated 20 Gb/s low power chip-level optical interconnects between fabricated chips, proving that this scheme can offer compact low-cost chip-level I/O solutions and have a significant impact on practical electronic-photonic integration in high performance computers (HPC), cpu-memory interface, 3D-IC, and LAN/SAN/data-center and network applications.
Advancement of silicon photonics technology can offer a new dimension in data communications with un-precedent bandwidth. Increasing the integration level in the silicon photonics is required to develop compact high-performance chip-level optical interconnects for future systems. Especially, monolithic integration of light source on a silicon wafer is important for future silicon photonic integrated circuits, since realizing a compact on-chip light source on a silicon wafer is a serious issue which impedes practical implementation of the silicon photonic interconnects. At present, due to the lack of a practical light source based on Group IV elements, flip chip-bonded or packaged lasers based on III–V semiconductor are usually being used as external light sources, to feed silicon modulators on SOI wafers to complete a photonic transmitter, except the reported silicon hybrid lasers monolithic-integrated on SOI wafers. To overcome above problem, we have proposed a compact on-chip light source, the directly monolithic-integrated VCSEL on a bulk silicon wafer (VCSEL-on-Si), based on the transplanted epitaxial film by substrate lift-off process and following device-fabrication on the bulk Si wafer. This can offer practical low-power-consumption light sources integrated on a silicon wafer, which can provide a complete chip-level I/O set when combined with monolithic-integrated vertical-illumination Ge-on-Si photodetectors on the same silicon wafer. In this work, we report the characterization of direct-modulation VCSELs-on-Si for λ ~850 nm with CW optical output power > ~2 mW and the threshold current < ~3 mA, over 10 Gb/s operations. We also discuss about the thermal characteristics of the VCSELs-on-Si.
Based on either a SOI wafer or a bulk-silicon wafer, we discuss silicon photonic devices and integrations for chip-level
optical interconnects. We present the low-voltage silicon PICs on a SOI wafer, where Si modulators and Ge-on-Si
photodetectors are monolithically-integrated for intra-chip or inter-chip interconnects over 40 Gb/s. For future chip-level
integration, the 50 Gb/s small-sized depletion-type MZ modulator with the vertically-dipped PN-depletion-junction
(VDJ) is also presented. We report vertical-illumination-type Ge photodetectors on bulk-silicon wafers, with high
performances up to 50 Gb/s. We present the bulk-silicon platform for practical implementation of chip-level
interconnects, and the performance of the photonic transceiver silicon chip.
We investigate the improvement of an insertion loss in silicon arrayed waveguide grating (AWG), by analyzing the
multimode generation due to the field-mismatching effect. 8 channel silicon AWGs on a 6” SOI wafer are fabricated
with an ultra-shallow etching structure and various aperture size of arrayed WGs. Our experimental results demonstrate
the improved insertion loss and crosstalk characteristics. The fabricated AWG shows an insertion loss less than 1 dB
with a crosstalk of -23.2 ~ -25.6 dB, exhibiting ~2.5 dB improvement of insertion loss and ~5 dB improvement of
crosstalk, compared to our reported result.
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