This paper demonstrates the successful lab-to-fab transition of dynamic secondary-ion mass spectrometry (SIMS). In comparison to traditional lab SIMS, the in-line version is optimized for automated wafer and measurement sequence handling and high throughput measurements in small areas. Key advantages are fast turn-around time, reduced scrap, increased yield, and the measured wafer can continue processing in the manufacturing line. The benefits of in-line SIMS in the production environment are demonstrated for several use cases: matching and monitoring the long-term stability of epitaxy tools on monitor wafers, process optimization and monitoring of epitaxial Si and SiGe layers on blanket and patterned wafers with blanket metrology targets, measurement of implant and dopant profiles on blanket and patterned wafers, and characterization of the Ge and B diffusion in multi-layer stacks stimulated by high-temperature annealing. Additionally, the characterization of the source/drain epitaxy in a fully integrated nanosheet gate-all-around transistor architecture is demonstrated and discussed. The results are compared to off-line lab SIMS and alternative methods where available.
To further enhance performance of in-line XPS metrology we will demonstrate the benefit of an unsupervised machine learning approach to increase precision of critical metal gate film thickness measurements and quantification of doping concentration within source-drain junctions. Unsupervised ML efficiently separates process information from inherent noise in the XPS spectra to enable a noise-filtering that improves result precision. The observed precision improvements were utilized to increase wafer through-put by reducing the acquisition time while preserving precision, accuracy, and sensitivity when supporting high volume manufacturing.
Machine learning (ML) techniques have been successfully deployed to resolve optical metrology challenges in semiconductor industry during recent years. With more advanced computing technology and algorithms, the ML system can be improved further to address High Volume Manufacturing (HVM) requirements. In this work, an advanced ML eco-system was implemented based on big data architecture to generate fast and user-friendly ML predictive models for metrology purposes. Application work and results completed by using this ML eco-system have revealed its capability to quickly refine solutions to predict both external reference data and to improve the throughput of conventional Optical Critical Dimension (OCD) metrology. The time-to-solution has been significantly improved and human operational time has also been greatly reduced. Results were shown for both front end and back end of line measurement applications, demonstrating good correlations and small errors in comparison with either external reference or conventional OCD results. The incremental retraining from this ML eco-system improved the correlation to external references, and multiple retrained models were analyzed to understand retraining effects and corresponding requirements. Quality Metric (QM) was also shown to have relevance in monitoring recipe performance. It has successfully demonstrated that with this advanced ML eco-system, streamlined ML models can be readily updated for high sensitivity and process development applications in HVM scenarios.
Voids in copper lines are a common failure mechanism in the back end of line (BEOL) of integrated circuits manufacturing, affecting chip yield and reliability. As subsequent process nodes continue to shrink metal line dimensions, monitoring and control of these voids gain more and more importance [1]. Currently, there is no quantitative in-line metrology technique that allows voids to be identified and measured. This work aims to develop a new method to do so, by combining scatterometry (also referred to as Optical Critical Dimension or Optical CD) and low-energy x-ray fluorescence (LE-XRF), as well as machine learning techniques. By combining the inputs from these tools in the form of hybrid metrology, as well as with the incorporation of machine learning methods, we create a new metric, referred to as Vxo, to characterize the quantity of void. Additionally, the results are compared with inline electrical test data, as higher amounts of voids were expected to increase the measured resistivity. This was not found to be the case, as the impact of the voids was much less of a factor than variation in the cross-sectional area of the lines.
KEYWORDS: Boron, Fin field effect transistors, Semiconducting wafers, Germanium, Silicon, 3D metrology, Epitaxy, Transistors, Process control, Metrology
The epitaxial growth of source/drain structures demands a process with tight control of boron and germanium composition to ensure consistent device performance. However, in-line monitoring of the epitaxial composition in FINFET structures has been one of the most difficult challenges for both process development and manufacturing. Traditional in-line monitoring schemes have relied heavily on critical dimension (CD) measurements, with no composition information. Instead, composition information was provided by offline analysis techniques such as secondary ion mass spectrometry (SIMS), which is destructive and does not measure the composition directly on the FinFET device structure. In this paper, we present results from in-line X-Ray Photoelectron Spectroscopy (XPS) measurements on FinFET structures. This technique is not only sensitive to individual element abundance but also gives information related to the local chemical environment. For this application we monitored silicon, germanium, and boron concentrations in SiGeB EPI source/drain 3D structure without interference from other structural features in the logic device. The in-line XPS measurement of PFET EPI boron and germanium performed in this way on the full structure transistor has been demonstrated to correlate with CMOS device performance, thus significantly reducing time to detect epitaxial composition drift or excursion.
Padraig Timoney, Taher Kagalwala, Edward Reis, Houssam Lazkani, Jonathan Hurley, Haibo Liu, Charles Kang, Paul Isbester, Naren Yellai, Michael Shifrin, Yoav Etzioni
KEYWORDS: Machine learning, Metrology, Metals, Copper, Back end of line, Semiconducting wafers, High volume manufacturing, Process control, Critical dimension metrology, Front end of line
In recent years, the combination of device scaling, complex 3D device architecture and tightening process tolerances have strained the capabilities of optical metrology tools to meet process needs. Two main categories of approaches have been taken to address the evolving process needs. In the first category, new hardware configurations are developed to provide more spectral sensitivity. Most of this category of work will enable next generation optical metrology tools to try to maintain pace with next generation process needs. In the second category, new innovative algorithms have been pursued to increase the value of the existing measurement signal. These algorithms aim to boost sensitivity to the measurement parameter of interest, while reducing the impact of other factors that contribute to signal variability but are not influenced by the process of interest. This paper will evaluate the suitability of machine learning to address high volume manufacturing metrology requirements in both front end of line (FEOL) and back end of line (BEOL) sectors from advanced technology nodes. In the FEOL sector, initial feasibility has been demonstrated to predict the fin CD values from an inline measurement using machine learning. In this study, OCD spectra were acquired after an etch process that occurs earlier in the process flow than where the inline CD is measured. The fin hard mask etch process is known to impact the downstream inline CD value. Figure 1 shows the correlation of predicted CD vs downstream inline CD measurement obtained after the training of the machine learning algorithm. For BEOL, machine learning is shown to provide an additional source of information in prediction of electrical resistance from structures that are not compatible for direct copper height measurement. Figure 2 compares the trench height correlation to electrical resistance (Rs) and the correlation of predicted Rs to the e-test Rs value for a far back end of line (FBEOL) metallization level across 3 products. In the case of product C, it is found that the predicted Rs correlation to the e-test value is significantly improved utilizing spectra acquired at the e-test structure. This paper will explore the considerations required to enable use of machine learning derived metrology output to enable improved process monitoring and control. Further results from the FEOL and BEOL sectors will be presented, together with further discussion on future proliferation of machine learning based metrology solutions in high volume manufacturing.
KEYWORDS: Scatterometry, Back end of line, Metrology, 3D metrology, 3D modeling, Dielectrics, Copper, Process control, Etching, Semiconducting wafers, Photomasks
Scaling of interconnect design rules in advanced nodes has been accompanied by a reducing metrology budget for BEOL process control. Traditional inline optical metrology measurements of BEOL processes rely on 1-dimensional (1D) film pads to characterize film thickness. Such pads are designed on the assumption that solid copper blocks from previous metallization layers prevent any light from penetrating through the copper, thus simplifying the effective film stack for the 1D optical model. However, the reduction of the copper thickness in each metallization layer and CMP dishing effects within the pad, have introduced undesired noise in the measurement. To resolve this challenge and to measure structures that are more representative of product, scatterometry has been proposed as an alternative measurement. Scatterometry is a diffraction based optical measurement technique using Rigorous Coupled Wave Analysis (RCWA), where light diffracted from a periodic structure is used to characterize the profile. Scatterometry measurements on 3D structures have been shown to demonstrate strong correlation to electrical resistance parameters for BEOL Etch and CMP processes. However, there is significant modeling complexity in such 3D scatterometry models, in particlar due to complexity of front-end-of-line (FEOL) and middle-of-line (MOL) structures. The accompanying measurement noise associated with such structures can contribute significant measurement error. To address the measurement noise of the 3D structures and the impact of incoming process variation, a hybrid scatterometry technique is proposed that utilizes key information from the structure to significantly reduce the measurement uncertainty of the scatterometry measurement. Hybrid metrology combines measurements from two or more metrology techniques to enable or improve the measurement of a critical parameter. In this work, the hybrid scatterometry technique is evaluated for 7nm and 14nm node BEOL measurements of interlayer dielectric (ILD) thickness, hard mask thickness and dielectric trench etch in complex 3D structures. The data obtained from the hybrid scatterometry technique demonstrates stable measurement precision, improved within wafer and wafer to wafer range, robustness in cases where 3D scatterometry measurements incur undesired shifts in the measurements, accuracy as compared to TEM and correlation to process deposition time. Process capability indicator comparisons also demonstrate improvement as compared to conventional scatterometry measurements. The results validate the suitability of the method for monitoring of production BEOL processes.
Device scaling has not only driven the use of measurements on more complex structures, in terms of geometry, materials, and tighter ground rules, but also the need to move away from non-patterned measurement sites to patterned ones. This is especially of concern for very thin film layers that have a high thickness dependence on structure geometry or wafer pattern factor. Although 2-dimensional (2D) sites are often found to be sufficient for process monitoring and control of very thin films, sometimes 3D sites are required to further simulate structures within the device. The measurement of film thicknesses only a few atoms thick on complex 3D sites, however, are very challenging. Apart from measuring thin films on 3D sites, there is also a critical need to measure parameters on 3D sites, which are weak and less sensitive for OCD (Optical Critical Dimension) metrology, with high accuracy and precision. Thus, state-ofthe-art methods are needed to address such metrology challenges. This work introduces the concept of Enhanced OCD which uses various methods to improve the sensitivity and reduce correlations for weak parameters in a complex measurement. This work also describes how more channels of information, when used correctly, can improve the precision and accuracy of weak, non-sensitive or complex parameters of interest.
Advanced technology nodes, 10 nm and beyond, employing multipatterning techniques for pitch reduction pose new process and metrology challenges in maintaining consistent positioning of structural features. A self-aligned quadruple patterning (SAQP) process is used to create the fins in FinFET devices with pitch values well below optical lithography limits. The SAQP process bears the compounding effects from successive reactive ion etch and spacer depositions. These processes induce a shift in the pitch value from one fin compared to another neighboring fin. This is known as pitch walking. Pitch walking affects device performance as well as later processes, which work on an assumption that there is consistent spacing between fins. In SAQP, there are three pitch walking parameters of interest, each linked to specific process steps in the flow. These pitch walking parameters are difficult to discriminate at a specific process step by singular evaluation technique or even with reference metrology, such as transmission electron microscopy. We will utilize a virtual reference to generate a scatterometry model to measure pitch walk for SAQP process flow.
Complexity of process steps integration and material systems for next-generation technology nodes is reaching unprecedented levels, the appetite for higher sampling rates is on the rise, while the process window continues to shrink. Current thickness metrology specifications reach as low as 0.1A for total error budget – breathing new life into an old paradigm with lower visibility for past few metrology nodes: accuracy. Furthermore, for advance nodes there is growing demand to measure film thickness and composition on devices/product instead of surrogate planar simpler pads. Here we extend our earlier work in Hybrid Metrology to the combination of X-Ray based reference technologies (high performance) with optical high volume manufacturing (HVM) workhorse metrology (high throughput). Our stated goal is: put more “eyes” on the wafer (higher sampling) and enable move to films on pattern structure (control what matters). Examples of 1X front-end applications are used to setup and validate the benefits.
Advanced technology nodes, 10nm and beyond, employing multi-patterning techniques for pitch reduction pose new process and metrology challenges in maintaining consistent positioning of structural features. Self-Aligned Quadruple Patterning (SAQP) process is used to create the Fins in FinFET devices with pitch values well below optical lithography limits. The SAQP process bares compounding effects from successive Reactive Ion Etch (RIE) and spacer depositions. These processes induce a shift in the pitch value from one fin compared to another neighboring fin. This is known as pitch walking. Pitch walking affects device performance as well as later processes which work on an assumption that there is consistent spacing between fins. In SAQP there are 3 pitch walking parameters of interest, each linked to specific process steps in the flow. These pitch walking parameters are difficult to discriminate at a specific process step by singular evaluation technique or even with reference metrology such as Transmission Electron Microscopy (TEM). In this paper we will utilize a virtual reference to generate a scatterometry model to measure pitch walk for SAQP process flow.
KEYWORDS: Copper, Chemical mechanical planarization, Scatterometry, Metrology, Semiconducting wafers, Resistance, Reactive ion etching, Etching, 3D modeling, Back end of line
Copper interconnects have been adopted in advanced semiconductor manufacturing due to benefits of reduced RC delay, cross talk and power consumption. With each technology node, interconnects reduce in size resulting in increased line resistivity, a critical metric in determining the device performance. Reactive Ion Etching (RIE) and Copper Chemical Mechanical Polishing (Cu CMP) are two of the key back end of the line (BEOL) processes that affect the interconnect performance. Due to variations from incoming processes and the inherent variability induced by these processes, dielectric trench depth and resulting copper line height variations that can potentially result from these processes have direct impact to RC delay.
Traditional inline metrology methods used are time consuming and do not provide the needed wafer level metrics. In addition, measurement of remaining dielectric thickness on solid pads is not a good representative of the actual device structures and has been inaccurate for process due to dishing of the copper pads. Efficient control of BEOL processes requires measurement of metal line thickness and other critical profile parameters from which resistance can be extracted. In order to relate BEOL process steps and understand their interactions, it is necessary to have a directly comparable measurement methodology on a similar measurement structure.
Over the past several years, scatterometry has been proven as the only metrology method to provide the full profile information of the Cu lines. Scatterometry is a diffraction based optical measurement technique using Rigorous Coupled Wave Analysis (RCWA), where light diffracted from a periodic structure is used to characterize the details of profile. Unique algorithms, such as Holistic Metrology can be used to make the scatterometry development process faster.
In this paper, we will present how scatterometry can be used to measure copper line height on 3D structures and how feed forward from RIE can be applied for control of Cu CMP process for 20nm technology node. The importance of incoming trench depth variations is demonstrated for CMP polish time control in order to stabilize the copper line height. Validation data is presented for different scatterometry models including accuracy, repeatability and DoE tracking. Electrical resistance is shown to correlate to the copper trench profile measured by scatterometry. The paper will demonstrate the capability for reducing copper line height variation and the correlation of the reducing trench height variation to improved stabilization of electrical resistance.
Advanced nodes require precise detection and control of intricate profile details – scatterometry is tool of choice for such requirements. Scatterometry is a model-based technique, and needs extensive reference metrology for qualification. Such reference measurements are costly, time-consuming and often destructive causing delays in deployment. With increasing number of scatterometry steps in flow, and the requirement to collect more reference data points to statistically qualify shrinking metrology specifications, the cost and time for reference metrology is exponentially increasing. This work is aimed to significantly reduce this need. We developed a novel methodology whereby scatterometry spectral information itself is used to predict “virtual” reference data. We qualify this methodology on several key applications from 20nm and 14nm node. We find that performance of solution developed using proposed methodology is indeed similar to performance of solution obtained using real reference data, thereby significantly reducing the lead time to develop scatterometry solutions.
Until now, metrologists had no statistics-based method to determine the sampling needed for an experiment before the start that accuracy experiment. We show a solution to this problem called inverse total measurement uncertainty (TMU) analysis, by presenting statistically based equations that allow the user to estimate the needed sampling after providing appropriate inputs, allowing him to make important “risk versus reward” sampling, cost, and equipment decisions. Application examples using experimental data from scatterometry and critical dimension scanning electron microscope tools are used first to demonstrate how the inverse TMU analysis methodology can be used to make intelligent sampling decisions and then to reveal why low sampling can lead to unstable and misleading results. One model is developed that can help experimenters minimize sampling costs. A second cost model reveals the inadequacy of some current sampling practices—and the enormous costs associated with sampling that provides reasonable levels of certainty in the result. We introduce the strategies on how to manage and mitigate these costs and begin the discussion on how fabs are able to manufacture devices using minimal reference sampling when qualifying metrology steps. Finally, the relationship between inverse TMU analysis and hybrid metrology is explored.
The accelerated pace of the semiconductor industry in recent years is putting a strain on existing dimensional metrology equipment (such as critical dimension-secondary electron microscopy, atomic force microscopy, scatterometry) to keep up with ever-increasing metrology challenges. However, a revolution appears to be forming with the recent advent of hybrid metrology (HM). We highlight some of the challenges and lessons learned when setting up a standard HM solution and describe the first-in-industry implementation of HM within a high-volume manufacturing environment.
When designing an experiment to assess the accuracy of a tool as compared to a reference tool, semiconductor metrologists are often confronted with the situation that they must decide on the sampling strategy before the measurements begin. This decision is usually based largely on the previous experience of the metrologist and the available resources, and not on the statistics that are needed to achieve acceptable confidence limits on the final result. This paper shows a solution to this problem, called inverse TMU analysis, by presenting statistically-based equations that allow the user to estimate the needed sampling after providing appropriate inputs, allowing him to make important “risk vs. reward” sampling, cost, and equipment decisions. Application examples using experimental data from scatterometry and critical dimension scanning electron microscope (CD-SEM) tools are used first to demonstrate how the inverse TMU analysis methodology can be used to make intelligent sampling decisions before the start of the experiment, and then to reveal why low sampling can lead to unstable and misleading results. A model is developed that can help an experimenter minimize the costs associated both with increased sampling and with making wrong decisions caused by insufficient sampling. A second cost model is described that reveals the inadequacy of current TEM (Transmission Electron Microscopy) sampling practices and the enormous costs associated with TEM sampling that is needed to provide reasonable levels of certainty in the result. These high costs reach into the tens of millions of dollars for TEM reference metrology as the measurement error budgets reach angstrom levels. The paper concludes with strategies on how to manage and mitigate these costs.
KEYWORDS: Metrology, Semiconducting wafers, Critical dimension metrology, Transmission electron microscopy, Etching, Process control, Reactive ion etching, Data modeling, High volume manufacturing
Metrology tools are increasingly challenged by the continuing decrease in the device dimensions, combined with complex disruptive materials and architectures. These demands are not being met appropriately by existing/forthcoming metrology techniques individually. Hybrid Metrology (HM) – the practice to combine measurements from multiple toolset types in order to enable or improve the measurement of one or more critical parameters – is being incorporated by the industry to resolve these challenges. Continuing our previous work we now take the HM from the lab into the fab. This paper presents the first-in-industry implementation of HM within a High Volume Manufacturing (HVM) environment. Advanced 3D applications are the first to use HM: 20nm Contact etch and 14nm FinFET poly etch. The concept and main components of this Phase-1 Host-based implementation are discussed. We show examples of communication protocols/standards that have been specially constructed for HM for sharing data between the metrology tools and fab host in GLOBALFOUNDRIES, as well as the HM recipe setup and HVM results. Finally we discuss our vision and phased progression/roadmap for Phase-2 HM implementation to fully reap the benefits of hybridization.
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