Metalenses are flat lenses made from thin films with sub-wavelength nano-optical structures that can be created using the same processes that have been developed for integrated circuit manufacturing. We present a workflow that simulates the manufacturing process and enables process engineers and optical designers to study the impact of manufacturing on metalens performance without waiting for multiple manufacture-and-test cycles. To demonstrate this workflow, we design several metalenses and characterize the impact of process variation on absolute focusing efficiency, transmission, and output electric field.
With the introduction of Augmented Reality, Virtual Reality, and Mixed Reality (AR/VR/MR) applications, the fabrication of photonics devices is approaching a high volume manufacturing level. To scale these products to consumer friendly dimensions, there is still significant shrink needed for many not yet available components such as ultrasmall cameras, metalenses, microdisplays, and combiner optics. AR/VR/MR optical components include metalenses patterned over large areas, and the fidelity of these patterns may have a significant impact on performance. In this study, we apply OPC to the design intent and examine the implication of various lithographic and correction techniques on metalens performance through simulation. In addition, we investigate the root causes of the manufacturing process variability and its impact on metalens functionality. These devices are analyzed by comparing light propagation through the simulated manufactured system using rigorous lithographic models to the optimal system based on the design intent. The study finds that the size and shape of meta-atoms have a different impact on optical performance, depending on the type of the metalens.
Integrated circuit performance has been limited by transistor performance for many process nodes. However, in advanced nodes where pitches reach 10s of nanometers in size, there is an increasing probability of cases where circuit timing may be limited by the resistance and capacitance of the device rather than the transistor. This means that metal layer patterning may have implications on device performance beyond reliability, shorts, and opens. Lithography variation can be effectively predicted using stochastic simulations, including layer overlay. Simulating many patterns stochastically produces insight into the performance of the lithography process over time. Etching and metallizing the pattern set in simulation then allows the study to extend to electrical simulations. The combined lithography and electrical simulation data can then be used together to improve process or pattern performance before constructing a reticle. These data also allow the engineering teams to address resist and capacitance issues that may impact device performance prior to tapeout. This paper will investigate the metal layers of a structure designed to emulate an advanced node logic circuit that uses a CFET transistor. The structure will be corrected with OPC, and each layer will be simulated to generate a large (100) set of stochastic patterns at multiple process conditions in focus, overlay, and exposure. Each of these patterns will then be etched in a modeled process and metalized with copper. Finally, resistance and capacitance measurements will be generated from circuit simulations. The output data will then be used to update the lithography process or the pattern to improve through process performance including electrical characteristics.
Stochastic defects in the photoresist profile are one of the main yield limiters in EUV lithography patterning. These stochastic defects can be, for example, local resist loss, resist profile footing, or resist scumming. A subset of these defects is transferred through the hardmask open (HMO) patterning, leading ultimately to electrical opens and shorts. We use on-wafer data and process recipes to inform a physical etch model of the HMO process. This model is tested and confirmed by comparison to additional on-silicon data. The established model provides a visualization of the defect transfer through individual process steps and highlights critical patterning steps that may limit electrical yield. For example, a change in in-situ deposition time is observed to be more sensitive than oxide open or planarization film open times both in the model and on-wafer. This provides us the insight to focus tuning deposition step times to reduce defectivity and improve process performance. Furthermore, this model provides insight into the type of defects which are eliminated during specific patterning steps, and the type of defects which are persistent and ultimately lead to electrical opens and shorts. To characterize these defects, we plant intentional defects with varying dimensions and study which ones stay through the entire HMO process and which ones are eliminated. This insight helps better understand the HMO process, which may lead in the future to further process improvements.
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