This paper presents advancement of ultra-high speed (UHS) global shutter CMOS image sensor technology exceeding 100M frames per second (fps). The development of key technologies toward the next generation UHS global shutter CMOS image sensor are overviewed, that includes high density analog memory integration, pixel-wise memory array architecture, and burst correlated double sampling (CDS) operation. By introducing the newly developed signal readout scheme with minimized pixel pulse transitions, a frame period of photo-electrons transit time is achieved. The fabricated chip prototyping a 3D stacked structure achieved 100Mfps with 80 record length and 125Mfps with 40 record length under room temperature without any cooling systems.
Ultra-high speed (UHS) CMOS image sensors with on-chop analog memories placed on the periphery of pixel array for the visualization of UHS phenomena are overviewed in this paper. The developed UHS CMOS image sensors consist of 400H×256V pixels and 128 memories/pixel, and the readout speed of 1Tpixel/sec is obtained, leading to 10 Mfps full resolution video capturing with consecutive 128 frames, and 20 Mfps half resolution video capturing with consecutive 256 frames. The first development model has been employed in the high speed video camera and put in practical use in 2012. By the development of dedicated process technologies, photosensitivity improvement and power consumption reduction were simultaneously achieved, and the performance improved version has been utilized in the commercialized high-speed video camera since 2015 that offers 10 Mfps with ISO16,000 photosensitivity. Due to the improved photosensitivity, clear images can be captured and analyzed even under low light condition, such as under a microscope as well as capturing of UHS light emission phenomena.
Challenges and opportunities of ultraviolet (UV), visible (VIS) and near-infrared (NIR) light imaging technologies are overviewed in this paper. For light detectors and image sensors for UV/VIS/NIR imaging, it is required that they have high sensitivity for wide spectral light waveband or targeted narrow waveband as well as the high stability of light sensitivity toward UV light based on cost effective technology. Wide spectral response, high sensitivity and high stability advanced Si photodiode (PD) pn junction formation technology based on the flattened Si surface and high transmittance on-chip optical filter formation technology were developed. A linear photodiode array (PDA), wide dynamic range and ultrahigh speed CMOS image sensors employing the developed technology were fabricated and their advanced performances are described in this paper.
In this paper, we demonstrate that the floating capacitor load readout operation has higher readout gain and wider
linearity range than conventional pixel readout operation, and report the reason. The pixel signal readout gain is
determined by the transconductance, the backgate transconductance and the output resistance of the in-pixel driver
transistor and the load resistance. In floating capacitor load readout operation, since there is no current source and the
load is the sample/hold capacitor only, the load resistance approaches infinity. Therefore readout gain is larger than that
of conventional readout operation. And in floating capacitor load readout operation, there is no current source and the
amount of voltage drop is smaller than that of conventional readout operation. Therefore the linearity range is enlarged
for both high and low voltage limits in comparison to the conventional readout operation. The effect of linearity range
enlargement becomes more advantageous when decreasing the power supply voltage for the lower power consumption.
To confirm these effects, we fabricated a prototype chip using 0.18um 1-Poly 3-Metal CMOS process technology with
pinned PD. As a result, we confirmed that floating capacitor load readout operation increases both readout gain and
linearity range.
We evaluated effective time constants of random telegraph noise (RTN) with various operation timings of in-pixel
source follower transistors statistically, and discuss the dependency of RTN time constants on the duty ratio (on/off ratio) of MOSFET which is controlled by the gate to source voltage (VGS). Under a general readout operation of CMOS image sensor (CIS), the row selected pixel-source followers (SFs) turn on and not selected pixel-SFs operate at different bias conditions depending on the select switch position; when select switch locate in between the SF driver and column output line, SF drivers nearly turn off. The duty ratio and cyclic period of selected time of SF driver depends on the operation timing determined by the column read out sequence. By changing the duty ratio from 1 to 7.6 x 10-3, time constant ratio of RTN (time to capture <τc<)/(time to emission <τe<) of a part of MOSFETs increased while RTN amplitudes were almost the same regardless of the duty ratio. In these MOSFETs, <τc< increased and the majority of <τe< decreased and the minority of <τe< increased by decreasing the duty ratio. The same tendencies of behaviors of <τc< and <τe< were obtained when VGS was decreased. This indicates that the effective <τc< and <τe< converge to those under off state as duty ratio decreases. These results are important for the noise reduction, detection and analysis of in pixel-SF with RTN.
In this paper, we demonstrate the technologies related to the pixel structure achieving the fully charge transfer time of less than 10 nsec for the 20M frame per second burst CMOS image sensor. In this image sensor, the size of the photodiode (PD) is 30.0 μmH x 21.3 μmV in the 32.0 μmH x 32.0 μmV pixel. In the pixel, the floating diffusion (FD) and the transfer-gate-electrode (TG) are placed at the bottom center of the PD. The n-layer for the PD consists of the semicircular regions centered on the FD and the sector-shaped portions extending from the edges of the semicircular regions. To generate an electric field greater than the average of 400 V/cm toward the FD direction in the entire PD region, the n-layer width of the sector-shaped portions becomes narrower from the proximal-end to the distal-end. By using the PD structure, which includes the above mentioned n-layer shape and the PD dopant profile with the condition of three times n-type dopant implantation, we achieved to collect 96 % of the charges generated in the PD at the FD within 10 nsec. An ultra-high speed CMOS image sensor with the abovementioned pixel structure has been fabricated. Through the experiments, we confirmed three key characteristics as follows; the image lag was below the measurement limit, the electron transit time in the PD was less than 10 nsec, and the entire PD region had equivalent sensitivity.
In this paper, the ultra-high speed (UHS) video capturing results of time dependent dielectric breakdown (TDDB) of
MOS capacitors using the UHS camera with the maximum frame rate of 10M frame per second (fps) are reported. In
order to capture the breakdown, we set a trigger circuit which detects the rapid current increase through the MOS
capacitor. Some movies have succeeded to capture the intermittent light emissions on some points of the gate during the
breakdown. From the movies taken at 100K to 1M fps, the distribution centers of the light emission time and the period
were 10 sec and 30 μsec, respectively. From the movies taken at 10M fps, the light emission time and the period were
less than 10 μsec. The random failure mode has higher percentage of single light emissions than that of the wear-out
failure mode, indicating a correlation between of the light emission mode and the TDDB failure mode.
In this paper, we demonstrate two types of new photodiode array (PDA) with fast readout speed and high stability to
ultraviolet (UV) light exposure. One is a high full well capacity sensor specialized for absorption spectroscopy, the other
one is a high sensitivity sensor for emission spectroscopy. By introducing multiple readout paths along the long side of
the rectangle PD, both two PDAs have achieved more than 150 times faster readout speed compared with a general PDA
structure with a single readout path along the short side of PD. By introducing a photodiode (PD) structure with a thin
and steep dopant profile p+ layer formed on a flattened Si surface, a higher stability of the light sensitivity to UV light
exposure was confirmed compared with a general PD structure for conventional PDAs.
KEYWORDS: Analog electronics, Amplifiers, Interference (communication), CMOS sensors, Vacuum fluorescent displays, Cadmium sulfide, Voltage controlled current source, CMOS technology, Power supplies, Signal to noise ratio
This paper presents a new analog readout architecture for low-noise CMOS image sensors. A proposed forward noisecanceling
circuitry has been developed in our readout architecture to provide a sharper noise-filtering. The new readout
architecture consists of a column high-gain amplifier with correlated-double-sampling (CDS), a column forward noisecanceling
circuitry, and column sample-and-hold circuits. Through the high-gain amplifier together with the forward
noise-canceling circuitry, this readout architecture effectively reduces random noise of in-pixel source follower and
column amplifier as well as temporal line noise from power supplies and pulse lines. A prototype 400(H) x 250(V)
CMOS image sensor using the new readout architecture has been fabricated in a 0.18 μm 1-Poly 3-Metal CMOS
technology with pinned-photodiode. Both the pixel pitch and the column circuit pitch are 4.5 μm. The input-referred
noise of the new readout architecture is 37 μVrms, which has been reduced by 23 % compared to that of the conventional
readout architecture. The input-referred noise of the pixel with new readout architecture is 72 μVrms, which has been
reduced by 24 % compared to that of the pixel with conventional readout architecture.
Both static and low frequency temporal noise characteristics were statistically evaluated for in-pixel source followerequivalent
transistors with various channel types and body bias conditions. The evaluated transistor types were surface
channel (SC) and buried channel (BC) transistors with or without isolated wells. The gate width/length of the evaluated
transistors was 0.32/0.32 μm/μm and the gate oxide thickness was 7.6 nm. The BC transistors without isolated well
exhibit noise distribution having a much lower noise level and a steeper slope compared to the SC transistors. For the BC
transistors with isolated wells without body bias, the noise level increased compared to the BC transistors with body bias.
It has been confirmed that the amplitude of random telegraph noise has a correlation to subthreshold swing factor (SS)
for both BC and SC transistors. The increase of the noise level of BC transistors without body bias is due to the increase
of the SS originated from a stronger short channel effect.
In this work, by optimizing the structure and thickness of the on-chip multilayer dielectric stack using SiO2 and low
extinction coefficient Si3N4 with the high UV-light sensitivity photodiode technology, high external Q.E. and high
stability to UV-light were both successfully obtained. By changing the structure of on-chip multilayer dielectric stack
and film thickness, we obtained the photodiode with the high external Q.E. in the desired UV-light region.
In this paper, a CMOS image sensor using floating capacitor load readout operation has been discussed. The floating
capacitor load readout operation is used during pixel signals readout. And this operation has two features: 1. in-pixel
driver transistor drives load capacitor without current sources, 2. parasitic capacitor of pixel output vertical signal line is
used as a sample/hold capacitor. This operation produces three advantages: a smaller chip size, a lower power
consumption, and a lower output noise than conventional CMOS image sensors. The prototype CMOS image sensor has
been produced using 0.18 μm 1-Poly 3-Metal CMOS process technology with pinned photodiodes. The chip size is 2.5
mmH x 2.5 mmV, the pixel size is 4.5 μmH x 4.5 μmV, and the number of pixels is 400H x 300V. This image sensor
consists of only a pixel array, vertical and horizontal shift registers, column source followers of which height is as low as
that of some pixels and output buffers. The size of peripheral circuit is reduced by 90.2 % of a conventional CMOS
image sensor. The power consumption in pixel array is reduced by 96.9 %. Even if the power consumption of column
source follower is included, it reduced by 39.0 %. With an introduction of buried channel transistors as in-pixel driver
transistors, the dark random noise of pixels of the floating capacitor load readout operation CMOS image sensor is 168
μVrms. The noise of conventional image sensor is 466 μVrms; therefore, reduction of 63.8 % of noise was achieved.
We have developed a high accuracy color reproduction method based on an estimated spectral reflectance of objects
using additional virtual color filters for a wide dynamic range WRGB color filter CMOS image sensor. The four virtual
color filters are created by multiplying the spectral sensitivity of White pixel by gauss functions which have different
central wave length and standard deviation, and the virtual sensor outputs of those virtual filters are estimated from the
four real output signals of the WRGB image sensor. The accuracy of color reproduction was evaluated with a Macbeth
Color Checker (MCC), and the averaged value of the color difference ΔEab of 24 colors was 1.88 with our approach.
In this work, n+pn-type photodiodes with various surface n+ layer profiles formed on the atomically flat Si surface were
evaluated to investigate the relationships between the surface photo-generated carrier drift layer dopant profiles with a
high uniformity and sensitivity and stability to UV-light. The degradation mechanism of photodiode sensitivitiy in UVlight
wavelength due to UV-light exposure is explained by the changes in the fixed charges and the interface states at
Si/SiO2 system above photodiode. Finally, a design strategy of photodiode dopant profile to achieve a high sensitivity
and a high stability to UV-light is proposed.
In this paper, a high-speed CMOS image sensor having a new architecture and a new operating principle has been
developed. The image sensor achieves both the continuous capturing and the burst capturing by a single chip, and has
low power consumption, low heat generation, high sensitivity and high S/N ratio. This image sensor consist of mainly
four blocks, two dimensional pixel array of 4-transister CMOS active pixel, analog memory arrays connected with each
pixel output line independently to the pixel array, scanning circuits and multiple number of output amplifiers. A
prototype image sensor was fabricated using a 0.18μm 2-Poly 3-Metal CMOS technology with the die size of 5550 μmH
x 4575 μmV, the pixel size of 48 μmH x 48 μmV, the number of pixels of 72H x 32V, the number of analog memories of
104 memories per pixel and the 6 parallel horizontal output circuits and output amplifiers. The aperture ratio is 35% and
the conversion gain is 60 μV/e-(input referred). It has been confirmed that this image sensor achieves 10,000,000 fps
during burst capturing mode and 10,000 fps during the continuous capturing mode through the image capture
experiments of high speed phenomena such as rotating object and discharge phenomenon.
KEYWORDS: RGB color model, Image sensors, Color reproduction, CMOS sensors, Optical filters, Light sources, Signal processing, Signal to noise ratio, Interference (communication), Switches
We have developed a robust color reproduction methodology by a simple calculation with a new color matrix using the
formerly developed wide dynamic range WRGB lateral overflow integration capacitor (LOFIC) CMOS image sensor.
The image sensor was fabricated through a 0.18 μm CMOS technology and has a 45 degrees oblique pixel array, the 4.2
μm effective pixel pitch and the W pixels. A W pixel was formed by replacing one of the two G pixels in the Bayer RGB
color filter. The W pixel has a high sensitivity through the visible light waveband. An emerald green and yellow (EGY)
signal is generated from the difference between the W signal and the sum of RGB signals. This EGY signal mainly
includes emerald green and yellow lights. These colors are difficult to be reproduced accurately by the conventional
simple linear matrix because their wave lengths are in the valleys of the spectral sensitivity characteristics of the RGB
pixels. A new linear matrix based on the EGY-RGB signal was developed. Using this simple matrix, a highly accurate
color processing with a large margin to the sensitivity fluctuation and noise has been achieved.
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