This paper presents a design and technology co-optimization (DTCO) study of metal cut formation in the sub-20-nmregime. We propose to form the cuts by applying grapho-epitaxial directed self-assembly. The construction of a DTCO flow is explained and results of a process variation analysis are presented. We examined two different DSA models and evaluated their performance and speed tradeoff. The applicability of each model type in DTCO is discussed and categorized.
Pellicles that satisfy transmission, emission, thermal, and mechanical requirements are highly desired for EUV high volume manufacturing. We present here the capability of integrating pellicles in the full flow of rigorous EUV lithography simulations. This platform allows us to investigate new coherence effects in EUV lithography when pellicle is used. Critical dimension uniformity and throughput loss due to pellicle defects and add-on particles are also analyzed. Our study provides theoretical insights into pellicle development and facilitates pellicle insertion in EUV lithography.
KEYWORDS: 3D modeling, Calibration, Data modeling, Optical lithography, Nanotechnology, Very large scale integration, System on a chip, Logic, Research facilities
Direct Optimization (DO) of a 3D DSA model is a more optimal approach to a DTCO study in terms of accuracy and speed compared to a Cahn Hilliard Equation solver. DO’s shorter run time (10X to 100X faster) and linear scaling makes it scalable to the area required for a DTCO study. However, the lack of temporal data output, as opposed to prior art, requires a new calibration method. The new method involves a specific set of calibration patterns. The calibration pattern’s design is extremely important when temporal data is absent to obtain robust model parameters. A model calibrated to a Hybrid DSA system with a set of device-relevant constructs indicates the effectiveness of using nontemporal data. Preliminary model prediction using programmed defects on chemo-epitaxy shows encouraging results and agree qualitatively well with theoretical predictions from a strong segregation theory.
Extreme ultraviolet (EUV) lithography at 13.5 nm stands at the crossroads of next generation patterning technology for high volume manufacturing of integrated circuits. Photo resist models that form the part of overall pattern transform model for lithography play a vital role in supporting this effort. The physics and chemistry of these resists must be understood to enable the construction of accurate models for EUV Optical Proximity Correction (OPC). In this study, we explore the possibility of improving EUV photo-resist models by directly correlating the parameters obtained from experimentally measured atomic scale physical properties; namely, the effect of interaction of EUV photons with photo acid generators in standard chemically amplified EUV photoresist, and associated electron energy loss events. Atomic scale physical properties will be inferred from the measurements carried out in Electron Resist Interaction Chamber (ERIC). This study will use measured physical parameters to establish a relationship with lithographically important properties, such as line edge roughness and CD variation. The data gathered from these measurements is used to construct OPC models of the resist.
In this paper, we study the impact of topographic guide or template properties on pattern formation in a directed self-assembly (DSA) process. In particular, we investigate the relationship between free energy and defect generation or process robustness, and analyze the influence of guide affinity. The good correlation between experimental and simulation results confirms the role of certain setup parameters and process conditions on the DSA patterning.
Since completely defect-free masks will be hard to achieve, it is essential to have a good understanding of the printability of the native extreme ultraviolet (EUV) mask defects. In this work, we performed a systematic study of native mask defects to understand the defect printability they cause. The multilayer growth over native substrate mask blank defects was correlated to the multilayer growth over regular-shaped defects having similar profiles in terms of their width and height. To model the multilayer growth over the defects, a multilayer growth model based on a level-set technique was used that took into account the tool deposition conditions of the Veeco Nexus ion beam deposition tool. Further, the printability of the characterized native defects was studied at the SEMATECH-Berkeley Actinic Inspection Tool (AIT), an EUV mask-imaging microscope at Lawrence Berkeley National Laboratory. Printability of the modeled regular-shaped defects, which were propagated up the multilayer stack using level-set growth model, was studied using defect printability simulations implementing the waveguide algorithm. Good comparison was observed between AIT and the simulation results, thus demonstrating that multilayer growth over a defect is primarily a function of a defect’s width and height, irrespective of its shape.
KEYWORDS: Photomasks, Extreme ultraviolet, Multilayers, Chemical species, Extreme ultraviolet lithography, Inspection, Monte Carlo methods, Computer simulations, Waveguides, Transmission electron microscopy
The availability of defect-free masks is considered to be a critical issue for enabling extreme ultraviolet lithography (EUVL) as the next generation technology. Since completely defect-free masks will be hard to achieve, it is essential to have a good understanding of the printability of the native EUV mask defects. In this work, we performed a systematic study of native mask defects to understand the defect printability caused by them. The multilayer growth over native substrate mask blank defects was correlated to the multilayer growth over regular-shaped defects having similar profiles in terms of their width and height. To model the multilayer growth over the defects, a novel level-set multilayer growth model was used that took into account the tool deposition conditions of the Veeco Nexus ion beam deposition tool. The same tool was used for performing the actual deposition of the multilayer stack over the characterized native defects, thus ensuring a fair comparison between the actual multilayer growth over native defects, and modeled multilayer growth over regular-shaped defects. Further, the printability of the characterized native defects was studied with the SEMATECH-Berkeley Actinic Inspection Tool (AIT), an EUV mask-imaging microscope at Lawrence Berkeley National Laboratory (LBNL). Printability of the modeled regular-shaped defects, which were propagated up the multilayer stack using level-set growth model was studied using defect printability simulations implementing the waveguide algorithm. Good comparison was observed between AIT and the simulation results, thus demonstrating that multilayer growth over a defect is primarily a function of a defect’s width and height, irrespective of its shape. This would allow us to predict printability of the arbitrarily-shaped native EUV mask defects in a systematic and robust manner.
Electrical validation of through process optical proximity correction verification limits in 32-nm process technology is presented. Correlation plots comparing electrical and optical simulations are generated by weighting the probability of occurrence of each process conditions. The design of electrical layouts is extended to subdesign rules to force failure and derive better correlation between electrical and simulated outputs. Some of these subdesign rule designs amplify the failures induced by an exposure tool, such as optical aberrations. Observations in this regard are reported. Sensitivity with respect to dimensions, orientations, and wafer distribution are discussed in detail.
KEYWORDS: Photomasks, Data modeling, Calibration, 3D modeling, Semiconducting wafers, Scanning electron microscopy, Optical proximity correction, Photoresist processing, Process modeling, Silicon
To reduce cost, implant levels usually use masks fabricated with older generation mask tools, such
as laser writers, which are known to introduce significant mask errors. In fact, for the same implant
photolithography process, Optical Proximity Correction (OPC) models have to be developed
separately for the negative and positive mask tones to account for the resulting differences from the
mask making process. However, in order to calibrate a physical resist model, it is ideal to use single
resist model to predict the resist performance under the two mask polarities. In this study, we show
our attempt to de-convolute mask error from the Correct Positive (CP) and Correct Negative (CN)
tone CD data collected from bare Si wafer and derive a single resist model. Moreover, we also
present the predictability of this resist model over a patterned substrate by comparing simulated
CD/profiles against wafer data of various features.
KEYWORDS: 3D modeling, Critical dimension metrology, Data modeling, Process modeling, Scanning electron microscopy, Semiconducting wafers, Etching, Optical lithography, Printing, 3D image processing
In this paper we will demonstrate how a 3D physical patterning model can act as a forensic tool for OPC
and ground-rule development. We discuss examples where the 2D modeling shows no issues in printing
gate lines but 3D modeling shows severe resist loss in the middle. In absence of corrective measure, there is
a high likelihood of line discontinuity post etch. Such early insight into process limitations of prospective
ground rules can be invaluable for early technology development. We will also demonstrate how the root
cause of broken poly-line after etch could be traced to resist necking in the region of STI step with the help
of 3D models. We discuss different cases of metal and contact layouts where 3D modeling gives an early
insight in to technology limitations. In addition such a 3D physical model could be used for early resist evaluation and selection for required ground-rule challenges, which can substantially reduce the cycle time for process development.
Electrical validation of through process OPC verification limits in 32nm process technology is presented in this paper.
Correlation plots comparing electrical and optical simulations are generated by weighting the probability of occurrence
of each process conditions. The design of electrical layouts is extended to sub ground rules to force failure and derive
better correlation between electrical and simulated outputs. Some of these sub ground rule designs amplify the failures
induced by exposure tool, such as optical aberrations. Observations in this regard will be reported in the paper.
Sensitivity with respect to dimensions, orientations and wafer distribution will be discussed in detail.
In this paper, we report large scale three-dimensional photoresist model calibration and validation
results for critical layer models that span 32 nm, 28 nm and 22 nm technology nodes. Although
methods for calibrating physical photoresist models have been reported previously, we are unaware
of any that leverage data sets typically used for building empirical mask shape correction models. .
A method to calibrate and verify physical resist models that uses contour model calibration data sets
in conjuction with scanning electron microscope profiles and atomic force microscope profiles is
discussed. In addition, we explore ways in which three-dimensional physical resist models can be
used to complement and extend pattern hot-spot detection in a mask shape validation flow.
Complex Optical Proximity Correction (OPC) must be deployed to meet advanced lithography requirements. The OPC
models are used to convert input design shapes into mask data that often deviate significantly from both the initial design
and the final wafer image in resist. The process includes selective shape biasing, applying pattern-specific corrections,
and, possibly, modeling the effect at multiple exposure conditions. It is important to verify the results of the OPC model
and this is done by invoking OPC verification programs. The verification models identify points of failure to specific
criteria. Failure can be defined as the simulated resist dimension below which a feature will not survive additional
processing. Since these models are built for use in OPC verification, they may only be well-calibrated at feature sizes
near target. This can introduce uncertainties in the failure predictions. This paper will explore options for validating the
OPC verification models and methods. While wafer prints are an obvious source of feedback on the simulated results,
there are also options at mask level. In this paper, we study the effect of programmed defects at wafer level, mask level
and through OPC verification method. For each test case, five points in the process window space are chosen to provide
comparison data between OPC verification measurements, mask-level intensity contour measurements - e.g. Aerial
Image Microscope System (AIMS), and wafer measurement of patterned photoresist. The results permit correlation to
measurable metrics and provide an improved understanding of OPC verification validity.
As technology continues to shrink with tighter design rules, it becomes inevitable for the integrated process to demand a more stringent control over the in-line parameters. For multilevel interconnect, each processing step in the formation of every layer of via plug and metal interconnect impacts the overall performance and yield of the silicon wafer. The control of the process thus becomes even more challenging as more layers of interconnect are required to meet the speed performance and density requirements.
The lithography process for 0.25 micrometer metal masking faces the challenge of tight design rule. Island patterning and line-end shortening have become more important due to the zero or small contact/via enclosure. A full understanding of the process latitude is necessary to choose the right process for a certain metal layer of 0.25 micrometer technology. In this paper, we develop a methodology to evaluate and optimize a metal asking process based on a set of critical structures. By characterized the overlapping process window for these critical structures, a comprehensive process latitude can be defined. This methodology is applied to the optimization of stepper NA/PC setting and the selection between I-line and DUV processes.
CMP of Tungsten (W) in the wafer process flow pose a major challenge for robust stepper alignment, particularly at tighter design rules for 0.25 micron and beyond. Traditional alignment strategies based on optical diffraction often fail to provide alignment accuracy and consistency, as dictated by the tighter overlay budgets. Intensity based image analysis methods prove to be more successful in the alignment of metal CMP layers. In addition the noise reduction and signal processing capabilities of alignment sensors, the condition of the mark after W-CMP is vital for achieving good alignment. In this paper we report results from various alignment mark designs. The marks are designed to reduce the impact of CMP process variations on stepper alignment. Three types of alignment methods using laser diffraction, bright field imaging and laser interferometry techniques were investigated. The brightfield imaging alignment schemes provide the best results using a narrow trench mark separated by wider islands. Details of stepper alignment signals and overlay measurement results corresponding to some of the relevant mark design sand process variations are included in the paper.
High speed photographic systems like the image rotation camera, the Cranz Schardin camera and the drum camera are typically used for recording and visualization of dynamic events in stress analysis, fluid mechanics, etc. All these systems are fairly expensive and generally not simple to use. Furthermore they are all based on photographic film recording systems requiring time consuming and tedious wet processing of the films. Currently digital cameras are replacing to certain extent the conventional cameras for static experiments. Recently, there is lot of interest in developing and modifying CCD architectures and recording arrangements for dynamic scene analysis. Herein we report the use of a CCD camera operating in the Time Delay and Integration (TDI) mode for digitally recording dynamic scenes. Applications in solid as well as fluid impact problems are presented.
Time Delay and Integration imaging offers a complete solution to the peripheral inspection/imaging of rotating cylindrical objects. Coupled with simple structured light schemes, the deformation or surface contour of the cylindrical object is highlighted and quantified. High speed TDI facilitate inspection of fast rotating objects, a feature preferred in industrial inspection systems. Experiments presented here are performed at rotation speeds of upto 2500 RPM. The experimental setup, influence of various system parameters are discussed in this paper. Examples using a food powder can as the object is provided.
Keywords: Machine vision, Digital imaging, Visual inspection, Moire methods
Machine vision systems routinely utilize structured light techniques for identifying the shapes of defects of the objects under inspection. The basic principle of the method is that any height difference from a reference plane causes a shift in the projection line of light either to left or right and up or down in the image plane of the recording camera. The height difference if due to a defect on an otherwise regular surface will result in a deformed light pattern corresponding to the dimensions of the defect. Moire patterns generated from this deformed light pattern can quantify the defect size, depth and shape. Existing machine vision systems use these techniques for the inspection of flat surfaces. Curved surface inspection although significant remains more or less unexplored. This paper presents the application of a TDI (Time Delay and Integration) camera for defect visualization on curved objects. The TDI operation and some applications of high speed TDI imaging will also be discussed.
A low-cost dynamic polariscope is presented. The experimental arrangement is based on the delayed-microflash technique. A LED is used as the flash source. Dynamic photoelastic patterns are recorded after different time delays from the loading point using a CCD camera operating in the time-delay and integration mode. Unlike the conventional photographic techniques, the experiments need not be performed in total darkness. Digital recording provides instantaneous visualization of the patterns and rapid repeatability.
Two optical methods are proposed for shape measurement and defect detection of curved surfaces in the form of a complete 360-deg profile of the object. The first one is the standard structured light approach. Display of the resulting data is the emphasis of this section. The second approach uses modulated structured light with a scanning digital camera for faster and simpler data acquisition. Quantitative processing is done off-line while real-time moiré produces enhanced display of the defects for qualitative analysis.
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