Mr. Samee Ur Rehman Profile

Samee Ur Rehman

at ASML

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Publications (2)

Proceedings Article | 20 March 2020 Presentation + Paper

Process context based wafer level grouping control: an advanced overlay process correction designed for DRAM 1z nm node in high volume manufacturing

Linmiao Zhang, William Susanto, Katsumasa Takahashi, Albert Chen, Tim Tang, Yi Zou, Chenxi Lin, Simon Hastings, Samee Ur Rehman, Manouk Rijpstra, Alfonso Sun

Proceedings Volume 11325, 113251O (2020) https://doi.org/10.1117/12.2552823

KEYWORDS: Semiconducting wafers, Overlay metrology, Process control, Feedback control, Optical parametric oscillators, Control systems, High volume manufacturing, Data processing, Metrology, Optical lithography

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Proceedings Article | 24 March 2017 Paper

Reducing the impact of etch-induced pattern shift on overlay by using lithography and etch tool corrections

Michael Kubis, Rich Wise, Charlotte Chahine, Katja Viatkina, Samee Ur-Rehman, Geert Simons, Mircea Dusa, David Hellin, Daniel Sobieski, Wenzhe Zhang, Christiane Jehoul, Patrick Jaenen, Philippe Leray

Proceedings Volume 10147, 101470H (2017) https://doi.org/10.1117/12.2260000

KEYWORDS: Etching, Scanners, Semiconducting wafers, Optical lithography, Overlay metrology, Lithography, Immersion lithography, Metrology, Atomic force microscopy, Ions, Critical dimension metrology

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With shrinking design rules, the overall patterning requirements are getting aggressively tighter and tighter. For the 5-nm node and beyond, on-product overlay below 2.5nm is required. Achieving such performance levels will not only need optimization of scanner performance but a holistic tuning of all process steps. In previous work, it has been shown that process-induced pattern asymmetry has significant impact on overlay performance at wafer edge and can be partially compensated by applying high-order scanner corrections or optimizing metrology targets. Today, we present the reduction of process-induced pattern asymmetry in a tunable etch system and demonstrate the related on-product overlay improvement combined with scanner corrections.

In our work we utilize etch tools (Lam Kiyo® conductor etch systems) with proprietary edge tuning technology that can be used to reduce the etch-related asymmetry at the wafer edge. In combination to this unique method, we evaluate the impact of high order corrections per exposure field to compensate for process asymmetry at the wafer edge with a state-of-the-art 1.35 NA immersion scanner (NXT:1970Ci).

The study is done on dedicated test wafers with 10-nm logic node design. We use angle-resolved scatterometry (YieldStar® S-250), atomic force microscopy, and SEM cross-sections to characterize process asymmetry. We present experimental investigation of the effect of etch tuning and scanner corrections on the pattern shift and the resulting overlay. In particular, we present results showing a reduction of etch-induced pattern shift by 12nm at wafer radius 147mm.

Results show that asymmetry can be addressed by both, litho compensation and etch tuning, and bring on-product overlay down to the required level. We discuss the benefit of the correction techniques especially for thick hard mask layers (the pattern shift scales linear with hard mask thickness) and evaluate a combined correction scenario, where preventive etch tuning and feed-back based scanner corrections are used. We conclude that a holistic tuning of all process steps will be required to fulfill overlay requirements of future nodes.

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