As the semiconductor industry rapidly approaches the 3nm lithography node, on-product overlay (OPO) requirements have become tighter, which drives metrology performance enhancements to meet the reduction in overlay (OVL) residuals. The utilization of multiple measurement wavelengths in Imaging- Based Overlay (IBO) has increased in the past few years to meet these needs. Specifically, the color per layer (CPL) method allows for optimizing the OVL measurement conditions per layer, including focus, light, wavelength (WL), and polarization customization which enhance the metrology results. CPL is applicable for multiple technology segments (logic, foundry, DRAM, 3D NAND), relevant for different devices (DRAM high stack layers, NAND channel holes, etc.), and can work well for both thin and thick layers for standard and EUV lithography processes. In this paper, we will review the benefits of CPL for multiple DRAM and NAND critical layers. We will describe how CPL can contribute to measurement accuracy by quantifying the OVL residual reduction in comparison to single-wavelength (SWL) measurement conditions.
The Edge Placement Error (EPE) is growing concerns due to the complexity increases of process variation as the design rule shrinkage of DRAM device. The EPE is a well-accepted and construction metric which can be derived from CD, Overlay and LER measurements from more than patterning layers that concerned.
With the consideration of the data consistency and to create a unified method to serve as an industry standard we evaluated 3 approaches: equation based, polygon based, measurement based – to calculate / combine / measure the device EPE. Results will be discussed in the presentation
Critical dimension uniformity (CDU) control using dose correction is well established and has relied on traditional polynomial models like Zernike and Legendre for a long time. As process margins are shrinking and CD (and CDU) control becomes a significant contributor to edge placement error (EPE), the dose correction models need to be enhanced to represent the systematic behavior of the fingerprints more precisely. In this paper we show that many CD signatures over the exposure field or over the wafer cannot be corrected efficiently using classical polynomials. As the CD signatures can come from a variety of processes like etch, CVD, polish, or deposition, a flexible model approach is required. Furthermore, making the right decision when choosing the correct model order of the classical polynomial based model is complicated as we need to handle the balance between the degrees of freedom and minimizing the residuals. With this problem statement in mind, we introduce a novel radial basis function (RBF) modeling approach for dose corrections that can correct a wide range of signatures. The new modeling approach is verified on real CD signatures on product, reducing CDU significantly. Additionally, we demonstrate that this approach can make the life of the engineers easy again, as there are no prior decisions about model type and order needed.
In this paper, the rAIMTM (robust AIM) overlay target was investigated in terms of the stability versus the POR AIM® (Advanced Imaging Metrology) target used for imaging-based overlay (IBO) measurement at after development inspection (ADI). The targets were designed using KLA’s MTD AcuRate™, metrology target design software that performs simulations based on the optical properties related to relative permittivity and permeability about the material of each of the layers. Using advanced device layers, we studied the performance of the POR AIM target versus the newly designed rAIM target for imaging-based overlay measurements. For each target, we quantified the optical contrast, kernel signal, correctable modeled terms, total measurement uncertainty (TMU), and overlay (OVL) residuals from the modeled data through various wavelengths inside the Moiré effect regime in the case of rAIM. We demonstrate that there is an OVL measurement performance improvement using the rAIM target versus the POR AIM target. The measured optical properties of the rAIM target and comparison to the POR AIM target will be presented.
Overlay metrology plays a significant role in process and yield control for integrated circuit (IC) manufacturing. As the On-Product Overlay (OPO) in advance nodes is reduced to a few nanometers, a very small margin is left for measurement inaccuracy. We introduce a multi-wavelength (spectral) analysis and measurement method, capable of characterizing overlay inaccuracy signatures on the wafer, and quantifying and removing the inaccuracy portion of the overlay measurement, resulting in a more accurate measurement, better process control, and yield enhancement. This method was applied to SK hynix’s advanced process production wafers, demonstrating an enhancement in accuracy over single-wavelength based overlay measurements.
This paper reports the readiness of key EUV resist process technologies using Metal Oxide Resist (MOR) aiming for the DRAM application. For MOR, metal contamination reduction and CD uniformity (CDU) are the key performance requirements expected concerning post exposure bake (PEB). Based on years of experience with spin-on type Inpria MOR, we have designed a new PEB oven to achieve contamination mitigation, while keeping our high standard of CDU. The new bake oven was introduced in our coater and developer and evaluated using line/space patterns. As described in the results, exceptional CD uniformity was realized while exceeding the metal contamination specification. The new plate design also enabled a 30% reduction in dose-to-size without degradation of CDU when applying higher PEB temperature. Another challenge for the DRAM application in particular is pattern collapse as applied to pillar patterns. By optimization of several parameters, the pattern collapse margin extended the minimum CD by 13.8%. The result was achieved with a combination of SiC in place of SOG for under layer, thinner resist film thickness and a modified resist material, MOR-B. Finally, to achieve target yield performance, defectivity reduction is also an important task towards MOR application. An integrated approach is needed to realize scum free patterning because if metal residuals remain in the open space, they can cause yield-killing defects. By analyzing possible root causes of defect sources, we attempt to eliminate etch-masking scum layer present after conventional developer processing. By applying a post develop rinse including novel hardware for defect reduction, bridge defects were reduced up to 19% with new the technology.
In world-leading semiconductor manufacturing, the device feature size keeps on reducing and with it processes become more challenging in the next technology node. The On Product Overlay (OPO) budget is therefore required to reduce further. Alignment is one of the key factors in reducing overlay wafer to wafer (W2W) variations. To save product area and reduce scribe line width, small alignment mark is evaluated to achieve the similar results as reference mark and to optimize the OPO performance. In this work, we will show the experimental results of small alignment mark and investigate the on product overlay performance by simulation.
We developed a statistical method that can be applied to overlay metrology tools to improve performance and time-to-results (TTR) of multi-cycle optimization based on the brute force method. First, we evaluated full response surfaces for each combination of the discrete equipment settings and calculated desirability scores using a normalization function. Second, we combined gradient optimization techniques and response surface methodologies to find the important local maxima (center of the islands in quadratic contour) and stationary response points. Once all the stationary response points have been identified, users can choose to rank the solutions by quality or can choose to use analysis of variance (ANOVA) methods to determine which main effects and/or interactions are of interest. Two separate layers were evaluated and compared to the process of reference (POR) brute force method of optimization. Results showed that the best residuals values from recipes optimized using 1-cycle SPOC-based automatic recipe optimization (ARO) and ARO based on the 2- cycle Brute-Force strategy were comparable to known residuals values from the POR recipes. Moreover, SPOC-based ARO was performed with a TTR of under 2 hours, while a 2-cycle Brute-Force ARO typically took 6~ 20 hours depending on specific configurations. The vast reduction in optimization time is primarily attributed to the elimination of multi-cycle refinement, whose data collection dominated the previously observed TTR. In conclusion, we demonstrated the ability to reduce time to solution by a factor of 3 while maintaining or improving on overlay residuals compared to existing brute force methodologies.
In this paper, budget characterization and wafer mapping of the Edge Placement Error (EPE) is studied to manage and improve pattern defects with a use case selected from SK Hynix’s most advanced DRAM 1x nm product. To quantify EPE, CD and overlay were measured at the multiple process steps and then combined for the EPE reconstruction. Massive metrology was used to capture extreme statistics and fingerprint across the wafer. An EPE budget breakdown was performed to identify main contributors and their variations. The end result shows EPEmax is mostly driven by local CD and overlay components while EPE variation is dominated by overlay and global CD components. Beyond EPE budget, a novel EPE wafer mapping methodology is introduced to visualize the temporal and spatial EPE performance which captures variation not seen from CD and overlay. This enables root-cause analysis of the pattern defects, and provides a foundation towards a better process monitoring solution. For EPE improvement, serial CD and overlay optimization simulation was performed to verify opportunities for reduction of the EPE and variation using the available ASML applications. The potential improvement for this use-case was confirmed to be 4.5% compared to baseline performance.
Reduction in on product overlay (OPO) is a key component for high-end, high yield integrated circuit manufacturing. Due to the continually shrinking dimensions of the IC device elements it has become near-impossible to measure overlay on the device itself, driving the need to perform overlay measurements on dedicated overlay targets. In order to enable accurate measurement on grid (target) in terms of OPO matching, the overlay mark must be as similar as possible to the device in order to mimic the process impact on the device. Imaging-based optical overlay (IBO) provides the best accuracy and robustness for overlay metrology measurements for many process layers. To further optimize IBO performance, a new robust AIM (rAIM™) IBO target design was developed, using the Moiré effect. rAIM is implemented using significantly smaller pitches compared with the standard AIM® target, hence providing a more device-like target design. This new target design has the potential to improve target accuracy and robustness, to improve measurability, and to meet overlay basic performance requirements, such as total measurement uncertainty (TMU).
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