Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposures of a low-viscosity resist deposited by jetting technology onto the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Previous studies have demonstrated NIL resolution better than 10 nm, making the technology resolution suitable for the patterning of several generations of critical memory levels with a single mask.
Overlay is critical for advanced memory devices such as dynamic random-access memory and phase change memory. Both device types continue to scale, with expected half pitches down to 14 nm and beyond. Typical overlay budgets are on the order of 20% of the half pitch, meaning overlay requirements of <3 nm. Previously, we have employed systems (such as high-order distortion correction) to improve upon higher order distortion errors, thereby improving the overlay performance of our process.
Some process variables that are unique to NIL and that can be considered as process tunable variables include imprint force and tip/tilt of the imprint head relative to the wafer. These were identified to be significant variables to further improve the overlay and to achieve good overlay stability in a production run at throughput. We introduce these overlay tuning knobs for NIL and present the techniques and models to achieve stability of imprint force and tip/tilt in order to reduce both wafer to wafer variation as well as the field–field variation of these variables. Applying these techniques enables NIL to meet the overlay requirements for advanced memory device production.
The integration of a NIL into production for advanced memory devices will require compatibility with existing high-end optical lithography processes in order to meet the aggressive overlay performance specifications. To deliver such a demanding overlay specification, it is necessary for NIL to achieve reliable alignment and to expand its overlay error budget to include as many as higher-order error components along with their countermeasure options. In this paper, NIL overlay models have been developed to address alignment of full fields and partial fields.
Imprint lithography has been shown to be a promising technique for replication of nano-scale features. Jet and Flash Imprint Lithography* (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate.
There are many criteria that determine whether a particular technology is ready for wafer manufacturing. Included on the list are overlay, throughput and defectivity. The most demanding devices now require overlay of better than 4nm, 3 sigma. Throughput for an imprint tool is generally targeted at 80 wafers per hour. Defectivity and mask life play a significant role relative to meeting the cost of ownership (CoO) requirements in the production of semiconductor devices.
The purpose of this paper is to report the status of throughput and defectivity work and to describe the progress made in addressing overlay for advanced devices. In order to address high order corrections, a high order distortion correction (HODC) system is introduced. The combination of applying magnification actuation to the mask, and temperature correction to the wafer is described in detail and examples are presented for the correction of K7, K11 and K17 distortions as well as distortions on actual device wafers.
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