KEYWORDS: Field programmable gate arrays, Sensors, Analog to digital converters, Tunable filters, Receivers, Photon counting, Picosecond phenomena, Electronic filtering, Clocks, Signal detection
We present a Field-Programmable Gate Array (FPGA) implementation of a single photon-counting receive modem for a pulse position modulated signal. The modem is compliant with the Consultative Committee for Space Data Systems (CCSDS) High Photon Efficiency (HPE) Optical Communications Coding and Synchronization standard and is capable of a maximum data rate of 267 Mbps. The system is designed on a commercial off-the-shelf FPGA platform and utilizes superconducting nanowire single photon counting detectors, Analog to Digital Converters (ADCs) to sample the detectors, and two FPGAs. Symbol timing recovery, photon counting, convolutional deinterleaving, and codeword synchronization are performed in the first FPGA. The second FPGA performs iterative decoding on each codeword of the Serially Concatenated Pulse Position Modulated (SCPPM) signal. A digital filter is included to compensate for timing jitter of the detector, and the decoder throughput can be adjusted through reconfigurable parallelization. The decoder also implements a resource-efficient, algorithmic polynomial interleaver and deinterleaver. Both FPGAs can be reconfigured to switch between Pulse Position Modulation (PPM)-16 and PPM-32 with code rates 1/3, 1/2, and 2/3. In this paper, we describe the receiver architecture and FPGA implementation of the timing recovery loop and SCPPM decoder, FPGA utilization for the different modes, and receive modem characterization test results.
The National Aeronautics and Space Administration (NASA) Glenn Research Center (GRC) has developed a photon-counting optical ground receiver for pulse-position modulated signals. The real-time receiver system includes a fiber interconnect, superconducting nanowire single-photon detectors (SNSPDs), and a real-time field programmable gate array (FPGA) based receiver. The fiber interconnect and SNSPDs are implemented with two different configurations. In the first, a 7-channel few-mode fiber photonic lantern couples the light from the telescope to 7 single-pixel few-mode fiber coupled SNSPDs. In the second configuration, a few-mode fiber couples light to a 16-pixel monolithic SNSPD array. The real-time FPGA-based receiver performs combining of up to 16 SNSPD channels, symbol timing recovery, demodulation, and decoding. The system is scalable with data rates ranging from 20 Mbps to 267 Mbps. It is compliant with the Consultative Committee for Space Data Systems (CCSDS) Optical Communications Coding and Synchronization Standard. This standard will be used in NASA deep space and other low photon flux missions, such as in the Orion Artemis-2 Optical Communications System (O2O) demonstration, planned for the first crewed flight of Orion. This paper describes the scalable real-time optical receiver system and presents characterization test results.
Convolutional interleavers are used in many different communications systems to correct for burst errors due to atmospheric fades and scintillation. The interleaver size is related to the channel coherence time and the data rate. Small convolutional interleavers can be implemented in a field programmable gate array (FPGA) block random access memory (BRAM). However, large interleavers exceeding the size of the BRAM on the FPGA are necessary for channels with longer fades and higher data rates. Therefore, an implementation utilizing double data rate (DDR) memory external to the FPGA is necessary. Wide DDR memory data buses can make the use of DDR memory for convolutional interleavers inefficient when individual symbols are written to and read from the memory. DDR memory operational speeds can also limit the data rate of the interleaver. The Consultative Committee for Space Data Systems (CCSDS) Optical Communications High Photon Efficiency (HPE) standard utilizes a convolutional channel symbol interleaver. A previous implementation of the HPE standard utilized BRAM for the convolutional interleaver, but mission requirements for the upcoming Optical Artemis-2 Orion (O2O) communications demonstration dictate the use of an interleaver exceeding the size of the BRAM. An algorithm and method for implementing the convolutional interleaver in the FPGA with DDR memory is described in this paper.
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