Tool-induced shift (TIS) is a common method used to quantify measurement error or accuracy of an overlay (OVL) metrology tool and is often attributed to tool asymmetry issues. In a previous paper, we introduced Modeled-TIS (mTIS), a machine learning (ML) based algorithm to predict per-site TIS correction on Image- Based Overlay (IBO) measurements. Recently, we adapted mTIS to support the requirements of high-volume manufacturing (HVM) in 3D NAND production. During our work in an HVM environment, we observed that the mTIS model is sensitive to complex process variations and many tool states. Such variations can change the measurement distribution and deteriorate the mTIS accuracy and reliability over time. In this paper, we present an automatic retrain triggering mechanism (“Trigger”) to monitor and adaptively update mTIS. The proposed methodology incorporates statistical and unsupervised ML algorithms which automatically detect shifts in measurement distribution, and initiate data collection to continuously adjust the model to process variations and tool states. The proposed mechanism does not require periodic retraining but rather initiates data collection and model updates only when required. Trigger chooses the wafers which possess novel information reducing the number of wafers required for the training and time to the model, critical requirements for our customers. We demonstrate the mTIS results of Trigger on various 3D NAND layers running in production. Finally, our approach can also be applied to future ML-based solutions.
Tool Induced Shift (TIS) is a measurement error commonly used to measure the accuracy of metrology tools. TIS manifests in the difference in overlay (OVL) misregistration between measurements of the same target at 0ᴼ and 180ᴼ rotations. This inaccuracy is attributed to tool asymmetries and is commonly caused by lens aberrations, lens alignment, illumination alignment and the tool’s interaction with target asymmetries. TIS impacts tool Total Measurement Uncertainty (TMU) and tool-to-tool matching. In memory chips, particularly 3D NAND, TMU is limited by TIS distribution across wafer, as it depends on process stability and is amplified by high layer topology. Additionally, TIS is influenced by wafer-to-wafer and lot-to-lot process variation. TIS correction by direct measurement per site (TIS-onLink, ToL) incurs a heavy penalty to measurement throughput as it requires measuring each site twice. Alternatively, measuring TIS on a sparse subset of sites, interpolating to other sites (TIS-on-Parent, ToP), induces a lower throughput penalty but is not accurate enough in many cases. In a previous paper we introduced a new methodology to improve overlay measurement with minimum throughput impact - Modeled-TIS (mTIS). This approach uses Machine Learning (ML) algorithms to predict per-site TIS correction on Image-Based Overlay (IBO) measurements. This method gives near ToL TIS correction performance at ToP throughput penalty, or better, depending on the use case. In this paper, we describe some of the algorithmic adaptations we made to the original algorithm to work in a high-volume manufacturing (HVM) environment and present results of an HVM use case on 3D NAND production lots.
We developed a pattern collapse prevention method which does not use a surfactant rinse agent. The
pattern collapse phenomenon is commonly expressed by the stress applied on the pattern with key
components including "the surface tension of the rinse agent" and "contact angle between pattern
surface and rinse agent." Using a surfactant as a rinse agent is targeted at reducing "the surface
tension of the rinse agent."
The pattern collapse prevention method of focus in this report evaluates the "the drying rate of a
rinse agent" and "the accumulated stress on a pattern" in relation to the pattern collapse phenomenon.
By increasing the drying rate of the rinse agent, the integrated stress on the pattern is reduced
allowing for the pattern collapse prevention. Dramatically speeding-up the drying rate of rinse agent
by Accelerated Purge (AP) drying integrated into a photolithography track develop module and
without using a surfactant rinse agent we have confirmed the ability to control the pattern collapse
phenomenon. With AP drying we have also confirmed further defect reduction that would normally
result from rinse agent remaining on a wafer, which has been significantly improved by the
super-fast drying process. AP drying is a promising technology which can control pattern collapse
phenomenon without using a surfactant rinse agent with advantages in yield improvement, process
time reduction and chemical cost reduction.
In immersion lithography process, film stacking architecture will be necessary to avoid top coat film peeling. To
achieve suitable stacking architecture for immersion lithography process, an EBR process that delivers tightly controlled
film edge position and good uniformity around the wafer circumference is needed.
We demonstrated a new bevel rinse system on a SOKUDO RF3 coat-and-develop track for immersion lithography. The
performance of the new bevel rinse system for various wafer properties was evaluated. It was found that the bevel rinse
system has a good controllability of film edge position and good uniformity around the wafer circumference. The results
indicate that the bevel rinse system has a large margin for wafer centering accuracy, back side particles, wafer shape and
substrates with good film edge position controllability, uniformity and clean apex. The system has been demonstrated to
provide a suitable film stacking architecture for immersion lithography mass production process.
In immersion lithography process, film stacking architecture will be necessary due to film peeling. However, the
architecture will restrict lithographic area within a wafer due to top side EBR accuracy
In this paper, we report an effective film stacking architecture that also allows maximum lithographic area. This study
used a new bevel rinse system on RF3 for all materials to make suitable film stacking on the top side bevel. This
evaluation showed that the new bevel rinse system allows the maximum lithographic area and a clean wafer edge.
Patterning defects were improved with suitable film stacking.
Recently, pattern collapse is becoming one of the critical issues in semiconductor manufacturing and many works have been done to solve this issue1) 2). Since pattern collapse occurs when outer force onto the resist pattern such as surface tension, impact of rinse solution, etc. surpasses the resistance of the resist pattern such as mechanical strength, adhesion force between resist and substrate, it is considered effective for improvement of pattern collapse to control resist film properties by track process, i.e., optimization of the mechanical properties of the resist film and enhancement of the adhesion force between resist and substrate3) -5). In this study, we focused on the mechanical strength of the resist film and examined how post applied bake (PAB) condition affects the pattern collapse behavior. From ellipsometry measurement, it was found that increasing PAB time and temperature resulted in thickness reduction and refractive index increase, which suggested that the density of the resist film became high. Then we analyzed the mechanical strength of the resist film with the tip indentation method using atomic force microscope. It was found that the hardness of the resist film was affected by PAB conditions and regardless of PAB condition, hardened layer existed beneath the film surface. Finally, we carried out the measurements of loads to collapse 180nm resist dot patterns using the direct peeling with atomic force microscope tip (DPAT) method. Loads ranged from 600 to 2000nN overall and essentially increased as seen for indentation measurements when PAB temperature or time was increased, except some critical conditions. Through these evaluations using AFM, we succeeded in quantitatively evaluate the mechanical properties of the resist films processed with various PAB conditions. It was found that PAB condition obviously impacts on the hardness of the resist film and it is closely related to pattern collapse load.
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