KEYWORDS: Silicon, Transistors, 3D modeling, Calibration, Finite element methods, Instrument modeling, Composites, Back end of line, Metals, Device simulation
Potential challenges with managing mechanical stress and the consequent effects on device performance for advanced three-dimensional (3-D) IC technologies are outlined. The growing need in a simulation-based design verification flow capable of analyzing a design of 3-D IC stacks and detecting across-die out-of-spec variations in MOSFET electrical characteristics caused by the die thinning and stacking-induced mechanical stress is addressed. The development of a multiscale simulation methodology for managing mechanical stresses during a sequence of designs of 3-D IC dies, stacks, and packages is focused. A set of physics-based compact models for a multiscale simulation is proposed to assess the mechanical stress across the device layers in silicon chips stacked and packaged with the 2.5D interposer-based, and true 3-D through silicon via-based technology. A simulation flow is developed for the hot-spot checking in different types of devices/circuits such as digital, analog, analog matching, memory, IO, characterized by different sensitivities to the stress-induced mobility variations. A calibration technique based on fitting to measured electrical characteristics of the test-chip devices is presented. The limited characterization or measurement capabilities for 3-D IC stacks and a strict “good die” requirement make this type of analysis critical in order to achieve an acceptable level of functional and parametric yield.
A novel model-based algorithm provides a capability to control full-chip design-specific variation in pattern transfer caused by via/contact etch (VCE) processes. This physics-based algorithm is capable of detecting and reporting etch hot spots based on the fabrication-defined thresholds of acceptable variations in critical dimension (CD) of etched shapes. It can be used also as a tool for etch process optimization to capture the impact of a variety of patterns presented in a particular design. A realistic set of process parameters employed by the developed model allows using this novel VCE electronic design automation tool for design-aware process optimization in addition to the "standard" process-aware design optimization.
A novel model-based algorithm provides a capability to control full-chip design specific variation in pattern transfer
caused by via/contact etch processes. This physics based algorithm is capable of detecting and reporting etch hotspots
based on the fab defined thresholds of acceptable variations in critical dimension (CD) of etched shapes. It can be used
also as a tool for etch process optimization to capture the impact of a variety of patterns presented in a particular design.
A realistic set of process parameters employed by the developed model allows using this novel via-contact etch (VCE)
EDA tool for the design aware process optimization in addition to the "standard" process aware design optimization.
Quantum chemical calculations were employed to get insight into the mechanisms involved in plasma-induced nitridation of gate oxide that will suppress boron penetration. The roles played by the nitrogen cations and atoms were explored. It was shown that B interaction with siloxane rings that contain incorporated nitrogen yielded a larger energy gain than rings without nitrogen. This explains the chemical nature of the nitrogen-induced barrier effect. Monte Carlo simulations were used to simulate the necessary energy of incident N2 cations to produce the bond cleavage down to a particular depth in the amorphous SiO2 layer. A combination of the HPEM and PCMC codes were used to simulate nitrogen atomic and cation fluxes and their energy distributions at the wafer surface. Combining simulated cation fluxes and their energy distributions at the wafer surface. Combining simulated cation energies with PROMIS Monte Carlo simulation results make it possible to derive the plasma process parameters that will permit a desired level of nitridation to be reached.
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