In this paper we present the design and characterization of a micro 4f optical imaging system for the purpose of characterizing mesoscopic diffractive optical elements. To this end, we demonstrate the systems' ability to measure very small variation sin diffraction intensity with high resolution. Because the system is illuminated by both coherent and incoherent sources, we characterize the cutoff frequency and modulation transfer function to determine the spatial resolution of the system. The system is validated by comparing measured results to theoretical predictions.
As processor speeds rapidly approach the Gigahertz regime, the disparity between process time and memory access time plays an increasing roll in the overall limitation of processor performance. In addition, limitations in interconnect density and bandwidth serve to exacerbate current bottlenecks, particularly as computer architectures continue to reduce in size. To address these issues, we propose a 3D architecture based on through-wafer vertical optical interconnects. To facilitate integration into the current manufacturing infrastructure, our system is monolithically fabricate din the silicon substrate and preserves scale of integration by using meso-scopic diffractive optical elements (DOEs) for beam fan-out. We believe that this architecture can alleviate the disparity between processor speeds and memory access times while increasing interconnect density by at least an order of magnitude. We are current working to demonstrate a prototype system that consists of vertical cavity surface emitting lasers, diffractive optical elements, photodetectors, and memory units integrate don a single silicon substrate. To this end, we are currently refining our fabrication and analysis methods for the realization of meso-scopic DOEs. In this paper, we present our progress to date and demonstrate through-silicon optical data transmission using DOEs that were designed, fabricated, and characterized at the University of Delaware. We present the validation of our theoretical models for the design of such DOEs with experimental data and discuss applications for our proposed architecture including instruction level parallel processors and field programmable gate arrays.
In this paper we introduce a micro-optical architecture that uses meso-scopic diffractive optical elements (DOEs) as 3D interconnects in a memory system for high level instruction level parallelism (ILP) processors. By using meso-scopic DOEs we can rescue the scale of integration to the VLSI scale, ie.e., the micron scale, achieve submicron alignment tolerance, improve reliability due to monolithic integration, facilitate integration into the current manufacturing infrastructure, and offer the ability for higher bandwidth and high interconnect densities. To this end we are developing the component technologies needed to realize this system. In this paper we present our work in the development of a theoretical and experimental framework for the design and characterization of meso-scopic DOEs, preliminary experimental results of meso-scopic beam splitters, and a large scale demonstration of the ILP memory system.
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