A high-speed double delta sampling (DDS) circuit with pipelined structure for CMOS image sensor (CIS) is presented. Considering the low readout speed of the DDS circuit compare with correcting double sampling (CDS) circuit, We separate the main operation of DDS circuit into two steps, and run the two steps alternately in odd readout column and even readout column, which seems like the pipelined operation. Thus, the readout speed of the DDS will as twice as fast than the traditional DDS. The architecture and readout sequence of the new circuit are introduced in detail. Meanwhile simulation results indicate the proposed circuit can achieve a high speed performance.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.