An after etch overlay measurement on device is typically used as a reference overlay as this is what determines the final overlay. The delta between on target overlay from after develop (ADI) and this reference overlay on device after etch (AEI) is known as the metrology to device offset (MTD). As the fab overlay is controlled by a run-to-run control of ADI overlay, it is preferred to minimize the MTD. The MTD concept in overlay metrology has long been present in the industry and many ways to mitigate this problem have been adopted (such as designing overlay target at ADI that has a similarly low aberration response as the device, or dialing in a static offset between ADI and AEI overlay, etc.). As overlay margins continue to shrink, existing methods start to show gaps and are insufficient to suppress the MTD to an acceptable level on the few most critical overlay layers. In order to address this gap, we need to deploy a much wider solution space that provides an integrated design-lithography-etch solution. In order to characterize the MTD, (assuming that target design in ADI has already minimized aberration response delta between target and device), it is important to understand that there are two major components to MTD: (1) an inaccuracy in ADI overlay (metrology artifacts mostly due to the presence of target asymmetry) and (2) etch to litho offset due to any post ADI added effects such as etch induced expansion and/or stress release etc. However, the above two components are strongly coupled and traditional characterization methods have difficulty in separating their contribution to the measurement. In this technical paper we will discuss novel methods (data driven as well as model-based) to decouple these and multi-lot results will show that MTD can be further minimized compared to traditional static correction between ADI and AEI.
The on-product overlay roadmap demands an aggressive overlay requirement in the advanced node. Currently the on-product overlay is dominated by effects coming from wafer processing and overlay target detectability. Processing effects such as symmetric stack variation and asymmetric overlay target deformations are expected to become limiting for accurate overlay measurements in future nodes
. Increased accuracy requirements and overall complexity in product stacks require a sensor with a higher flexibility. To address this an advanced metrology system is introduced in the fab, providing full flexibility in the selection of measurement wavelengths. On top of the wavelength flexibility, the increased wavelength switching speed enables the use of asymmetry robust recipes by combining multiple wavelength measurements at each overlay target.
In this paper we will introduce a method to select the most accurate multi-wavelength recipe that provides significant improvement in accuracy compared to the best single wavelength recipe. We will introduce KPIs to monitor the health of the multi-wavelength measurement. The KPIs are reported per site indicating the accuracy for every measured point.
Additionally we will show our steps towards the recovery of the points flagged by multi-wavelength KPI by a combination of measuring more wavelengths and an accuracy guided region of interest selection.
EUV lithography enables the transition from multiple patterning in DUV back to single patterning in EUV, with the associated cost benefit. While imaging and patterning becomes easier with EUV, cross-platform overlay performance needs to be taken into account.
With quadruple patterning, the matching performance is driven by the platform capabilities, with platform specific fingerprints not contributing to the matching performance as they are similar for each layer. Introducing EUV automatically means we need to compensate for the differences in the platform fingerprints, as they bring a penalty in the DUV-EUV matching budget.
This paper will explain what the main overlay contributors in cross-platform matched machine overlay are and how they can be cancelled or reduced using additional correction measures, with the goal to reach below 2.0 nm cross matched machine overlay.
KEYWORDS: Overlay metrology, Semiconducting wafers, Etching, Polarization, Metrology, Scanning electron microscopy, Physics, Signal processing, Monte Carlo methods, Semiconductor manufacturing
Success of diffraction-based overlay (DBO) technique1,4,5 in the industry is not just for its good precision and low toolinduced shift, but also for the measurement accuracy2 and robustness that DBO can provide. Significant efforts are put in to capitalize on the potential that DBO has to address measurement accuracy and robustness. Introduction of many measurement wavelength choices (continuous wavelength) in DBO is one of the key new capabilities in this area. Along with the continuous choice of wavelengths, the algorithms (fueled by swing-curve physics) on how to use these wavelengths are of high importance for a robust recipe setup that can avoid the impact from process stack variations (symmetric as well as asymmetric). All these are discussed. Moreover, another aspect of boosting measurement accuracy and robustness is discussed that deploys the capability to combine overlay measurement data from multiple wavelength measurements. The goal is to provide a method to make overlay measurements immune from process stack variations and also to report health KPIs for every measurement. By combining measurements from multiple wavelengths, a final overlay measurement is generated. The results show a significant benefit in accuracy and robustness against process stack variation. These results are supported by both measurement data as well as simulation from many product stacks.
The optical coupling between gratings in diffraction-based overlay triggers a swing-curve1,6 like response of the target’s signal contrast and overlay sensitivity through measurement wavelengths and polarizations. This means there are distinct measurement recipes (wavelength and polarization combinations) for a given target where signal contrast and overlay sensitivity are located at the optimal parts of the swing-curve that can provide accurate and robust measurements. Some of these optimal recipes can be the ideal choices of settings for production. The user has to stay away from the non-optimal recipe choices (that are located on the undesirable parts of the swing-curve) to avoid possibilities to make overlay measurement error that can be sometimes (depending on the amount of asymmetry and stack) in the order of several “nm”. To accurately identify these optimum operating areas of the swing-curve during an experimental setup, one needs to have full-flexibility in wavelength and polarization choices. In this technical publication, a diffraction-based overlay (DBO) measurement tool with many choices of wavelengths and polarizations is utilized on advanced production stacks to study swing-curves. Results show that depending on the stack and the presence of asymmetry, the swing behavior can significantly vary and a solid procedure is needed to identify a recipe during setup that is robust against variations in stack and grating asymmetry. An approach is discussed on how to use this knowledge of swing-curve to identify recipe that is not only accurate at setup, but also robust over the wafer, and wafer-to-wafer. KPIs are reported in run-time to ensure the quality / accuracy of the reading (basically acting as an error bar to overlay measurement).
Kaustuve Bhattacharyya, Arie den Boef, Martin Jak, Gary Zhang, Martijn Maassen, Robin Tijssen, Omer Adam, Andreas Fuchs, Youping Zhang, Jacky Huang, Vincent Couraudon, Wilson Tzeng, Eason Su, Cathy Wang, Jim Kavanagh, Christophe Fouquet
KEYWORDS: Overlay metrology, Metrology, Time metrology, Target acquisition, Semiconducting wafers, Target detection, Etching, Back end of line, Scanners, Process control
High-end semiconductor lithography requirements for CD, focus and overlay control drive the need for diffraction-based metrology1,2,3,4 and integrated metrology5. In the advanced nodes, more complex lithography techniques (such as multiple patterning), use of multi-layer overlay measurements in process control, advanced device designs (such as advanced FinFET), as well as advanced materials (like hardmasks) are introduced. These pose new challenges for lithometro cycle time, cost, process control and metrology accuracy. In this publication a holistic approach is taken to face these challenges via a novel target design, a brand new implementation of multi-layer overlay measurement capability in diffraction-based mode and integrated metrology.
KEYWORDS: Overlay metrology, Metrology, Semiconducting wafers, Time metrology, Chemical mechanical planarization, Scanners, Diffraction, Thin film coatings, Tin, High volume manufacturing
Aggressive on-product overlay requirements in advanced nodes are setting a superior challenge for the semiconductor industry. This forces the industry to look beyond the traditional way-of-working and invest in several new technologies. Integrated metrology2, in-chip overlay control, advanced sampling and process correction-mechanism (using the highest order of correction possible with scanner interface today), are a few of such technologies considered in this publication.
Reducing the size of metrology targets is essential for in-die overlay metrology in advanced semiconductor
manufacturing. In this paper, μ-diffraction-based overlay (μDBO) measurements with a YieldStar metrology tool are
presented for target-sizes down to 10 × 10 μm2. The μDBO technology enables selection of only the diffraction
efficiency information from the grating by efficiently separating it from product structure reflections. Therefore, μDBO
targets -even when located adjacent to product environment- give excellent correlation with 40 × 160 μm2 reference
targets. Although significantly smaller than standard scribe-line targets, they can achieve total-measurement-uncertainty
values of below 0.5 nm on a wide range of product layers. This shows that the new μDBO technique allows for accurate
metrology on ultra small in-die targets, while retaining the excellent TMU performance of diffraction-based overlay
metrology.
In keeping up with the tightening overall budget in lithography, metrology requirements have reached a deep subnanometer
level [1]. This drives the need for clean metrology (resolution and precision). Results have been
published of a thorough investigation of a scatterometry-based platform from ASML [7], showing promising
results on resolution, precision, and tool matching for overlay, CD and focus [2 - 6].
But overall requirements are so extreme that all measures must be taken in order to meet them. In light of this, in
addition to above-mentioned need for resolution and precision, the speed and sophistication in communication
between litho and metrology (feedback control) are also becoming increasingly crucial. An effective sampling
strategy for metrology plays a big role in order to achieve this.
This study discusses results from above mentioned scatterometry-based platform in light of sampling optimization.
For overlay, various sampling schemes (dense / sparse combinations as well as inter and intra field schemes) were
used on many production lots. The effectiveness of such sample schemes were studied to reveal an ideal sampling
scheme that can result in 0.5nm to 1nm gain in overlay control (compare to today's practice). Moreover, cycle time
contribution of metrology (at litho) in overall cycle time of a full process flow was investigated and quantified with
the concept of integrated metrology. Results indicate a cycle time reduction per layer (if an integrated concept is
used) of 3 to 5 hours, which can easily add up to several days of total cycle time reduction for a fab.
mmunication between lithography and metrology is becoming increasingly demanding in advanced nodes. This is where the requirements for metrology become extremely tight. This work is dedicated to the search for "clean" metrology that is required to address these requirements. Metrology measurements are obtained via an angle-resolved scatterometry-based platform (called YieldStar). Details of the technology behind YieldStar were thoroughly discussed by Vanoppen et al. in 2010. In this current work, measurement limits are challenged to test resolution and measurement uncertainty for overlay, critical dimension (CD), and sidewall angle (focus). Results indicate an atomic-scale performance of deep subnanometers. Two different sizes of scatterometry-based overlay targets are evaluated and compared using a technique called the similarity index. A CD reconstruction model is tested for cross talk of underlying thin-film layers, specifically the case where one of the underlying layers is anisotropic. A systematic approach is taken to increase the complexity of a CD reconstruction model in steps to evaluate the capability of handling birefringence effects of anisotropic material in the model. CD metrology data (1-D and 2-D/hole layers) are compared to CD scanning electron microscope data. Focus measurements are also extended for product wafers, and focus precision is evaluated. In addition, CD metrology monitor wafer applications, such as hotplate monitoring and overlay metrology monitor wafer application for scanner stability and matched machine overlay, are tested.
KEYWORDS: Overlay metrology, Metrology, Semiconducting wafers, Scanners, Back end of line, Lithography, 3D metrology, Finite element methods, Scatterometry, Critical dimension metrology
Advanced lithography is becoming increasingly demanding when speed and sophistication in communication
between litho and metrology (feedback control) are most crucial. Overall requirements are so extreme that all
measures must be taken in order to meet them. This is directly driving the metrology resolution, precision and
matching needs in to deep sub-nanometer level as well as driving the need for higher sampling (throughput).
Keeping the above in mind, a new scatterometry-based platform (called YieldStar) is under development at
ASML. Authors have already published results of a thorough investigation of this promising new metrology
technique which showed excellent results on resolution, precision and matching for overlay, as well as basic and
advanced capabilities for CD. In this technical presentation the authors will report the newest results taken from
YieldStar. This new work is divided in two sections: monitor wafer applications and product wafer applications.
Under the monitor wafer application: overlay, CD and focus applications will be discussed for scanner and track hotplate control. Under the product wafer application: first results from integrated metrology will be reported followed by poly layer and 3D CD reconstruction results from hole layers as well as overlay-results from small (30x60um), process-robust overlay targets are reported.
KEYWORDS: Overlay metrology, Semiconducting wafers, Metrology, Scanners, Lithography, Back end of line, Metals, Scatterometry, Front end of line, Signal to noise ratio
Advanced lithography is becoming increasingly demanding when speed and sophistication in communication
between litho and metrology (feedback control) are most crucial. Overall requirements are so extreme that all
measures must be taken in order to meet them. This is directly driving the metrology resolution, precision and
matching needs in to deep sub-nanometer level [4].
Keeping the above in mind, a new scatterometry-based platform is under development at ASML. Authors have
already published results of a thorough investigation of this promising new metrology technique which showed
excellent results on resolution, precision and matching for overlay, as well as basic and advanced capabilities for
CD [1], [2], [3]. In this technical presentation the authors will report the newest results from this ASML platform.
This new work was divided in two sections: monitor wafer applications (scanner control - overlay, CD and focus)
and product wafer applications.
A new metrology technique is being evaluated to address the need for accuracy, precision, speed and sophistication in metrology in near-future lithography. Attention must be paid to these stringent requirements as the current metrology capabilities may not be sufficient to support these near future needs. Sub-nanometer requirements in accuracy and precision along with the demand for increase in sampling triggers the need for such evaluation.
This is a continuation of the work published at SPIE Asia conference, 2008. In this technical presentation the authors would like to continue on reporting the newest results from this evaluation of such technology, a new scatterometry based platform under development at ASML, which has the potential to support the future needs.
Extensive data collection and tests are ongoing for both CD and overlay. Previous data showed overlay performance on production layers [1] that meet 22 nm node requirements. The new data discussed in this presentation is from further investigation on more process robust overlay targets and smaller target designs. Initial
CD evaluation data is also discussed.
The etch loading effect from wafer center to wafer edge results in worse Bit-line Contact layer (CB) to Gate Conductor layer (GC) overlay alignment performance at the wafer edge which directly impacts device yield. One workaround for this is to introduce additional image shifts during exposure at the edge of the wafer however this will reduce throughput due to the extra time required for wafer measurement (additional leveling scans) and extra exposure time (additional image). We demonstrate a new method which can avoid this overhead using Correction Per Exposure (CPE).
We are proposing to use CPE with manually generated overlay corrections. In this way, we are achieving the necessary wafer-edge overlay compensation, and there is no throughput-loss because there is no extra-routing.
Need for accuracy, precision, speed and sophistication in metrology has increased tremendously over the past few
years. Lithography performance will increasingly depend on post patterning metrology and this dependency will
be heavily accelerated by technology shrinkage. These requirements will soon become so stringent that the
current metrology capabilities may not be sufficient to support these near future needs. Accuracy and precision
requirements approaching well into sub-nanometer range while the demand for increase in sampling also
continues, triggering the need for a new technology in this area.
In this technical presentation the authors would like to evaluate such technology that has the potential to support
the future needs. Extensive data collection and tests are ongoing for both CD and overlay. Data on first order
diffraction based overlay shows unprecedented measurement precision. The levels of precision are so low that for
evaluation special methods has been developed and tested. In this paper overlay measurement method and data
will be discussed, as well as applicability for future nodes and novel lithography techniques. CD data will be
reported in the future technical publications.
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