Special Section on Advanced Plasma-Etch Technology

Pattern transfer of directed self-assembly patterns for CMOS device applications

[+] Author Affiliations
Hsin-Yu Tsai, Hiroyuki Miyazoe, Sebastian Engelmann, Lynne Gignac, James Bucchignano, David Klaus, Chris Breslin, Eric Joseph, Michael Guillorn

IBM Watson Research Center, 1101 Kitchawan Road, Yorktown, New York 10598

Chi-Chun Liu

IBM Albany Nanotech Research Center, 257 Fuller Road, Albany, New York 12203

Joy Cheng, Daniel Sanders

IBM Almaden Research Center, 650 Harry Road, San Jose, California 95120

J. Micro/Nanolith. MEMS MOEMS. 12(4), 041305 (Sep 25, 2013). doi:10.1117/1.JMM.12.4.041305
History: Received June 21, 2013; Revised August 19, 2013; Accepted August 27, 2013
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Abstract.  A study on the optimization of etch transfer processes using 200-mm-scale production type plasma etch tools for circuit relevant patterning in the sub-30-nm pitch regime using directed self-assembly (DSA) line–space patterning is presented. This work focuses on etch stack selection and process tuning, such as plasma power, chuck temperature, and end point strategy, to improve critical dimension control, pattern fidelity, and process window. Results from DSA patterning of gate structures featuring a high-k dielectric, a metal nitride and poly Si gate electrode, and a SiN capping layer are also presented. These results further establish the viability of DSA pattern generation as a potential method for Complementary metal–oxide–semiconductor (CMOS) integrated circuit patterning beyond the 10-nm node.

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© 2013 Society of Photo-Optical Instrumentation Engineers

Citation

Hsin-Yu Tsai ; Hiroyuki Miyazoe ; Sebastian Engelmann ; Chi-Chun Liu ; Lynne Gignac, et al.
"Pattern transfer of directed self-assembly patterns for CMOS device applications", J. Micro/Nanolith. MEMS MOEMS. 12(4), 041305 (Sep 25, 2013). ; http://dx.doi.org/10.1117/1.JMM.12.4.041305


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