The generated across-die distributions of stress components make it possible to calculate the averaged stress components inside transistor channels by using a simple interpolation procedure. However, at a device scale, the composite nature of the device layer becomes important. In fact, this layer represents a sequence of silicon islands separated by the shallow trench isolation (STI) regions filled by deposited silicon oxide. Keeping in mind a drastic difference in the mechanical characteristics of silicon and silicon oxide, as well as the fact that both the Si islands (i.e., the regions where the transistors are located) and STI regions are characterized by wide dispersion in sizes and shapes, we can conclude that strain distribution should depend on the local layout configurations of the device layer. FEA-based die-scale simulations of the CPI stress described in Sec. 2.3 cannot resolve the billions of shapes existing in devices layout. Therefore, in the next step of the multiscale simulation flow, a compact model-based calculation of the device-scale stress variations should be performed. This compact model considers the strain/stress distribution, calculated with Eq. (9), as an intial distribution that should be changed (relaxed) in accordance with the layout geometries. To calculate this stress redistribution, each transistor channel and the neighboring layout are portitioned on a set of “cut-layers” (both in $x$- and $y$-directions). Each cut-layer consists of the device layer and the silicon bulk, as shown in Fig. 6(a). The device layer consists of the sequence of segments representing slices of silicon islands and STIs separating silicon islands. Each $i$’th segment in the device “composite” layer is characterized by its length $Li$, Young’s modulus $Ei$ and Poisson’s ratio $\nu i$. The stresses given by Eq. (9) are considered as the “initial” stresses in each segment of the cutline. The difference in elastic properties of the neighbouring segments results in redistribution of this stress: each segment edge experiences additional lateral displacement $ui\u2032$ due to the action of the forces $Fi\u223c(1\u2212ESTI/ESi)\sigma iinit$. These displacements can be obtained from the solution of the force balance equation that takes into account the interaction between adjacent segments and the traction with the silicon bulk. Initial stress redistribution can be described as generation of an additional stress $\sigma '$, which can be obtained from solution of the corresponding force balance equation. For example, for each cut-layer directed along $x$-axis, the force balance equation for calculating the stress component $\sigma x\u2032$ is the following Display Formula
$\u2202\sigma x\u2032\u2202x+\u2202\tau xz\u2032\u2202z=0,$(10)
where $\tau xz$ is the shear stress component. Assuming that the vertical displacements everywhere in the plane are small in comparison with the lateral displacements, we can employ the following representation of stresses as functions of displacements Display Formula$\sigma x\u2032=E1\u2212\nu 2\u2202ux\u2032\u2202x\tau xz\u2032=E2(1+\nu )\u2202ux\u2032\u2202z.$(11)