Field-programmable gate array implementation of a systolic architecture for a morphology engine

Abdelaziz Chihoub; M. LaValva; J. Avins; Jeff Turlip

doi:10.1117/12.150276

6 August 1993 Field-programmable gate array implementation of a systolic architecture for a morphology engine

Abdelaziz Chihoub, M. LaValva, J. Avins, Jeff Turlip

Proceedings Volume 2064, Machine Vision Applications, Architectures, and Systems Integration II; (1993) https://doi.org/10.1117/12.150276
Event: Optical Tools for Manufacturing and Advanced Automation, 1993, Boston, MA, United States

Abstract

While morphology use is gaining in popularity, it can be a computationally intensive process. This is particularly true for applications requiring large structuring elements. In this paper we will describe the use of field programmable gate arrays (Xilinx 4000 FPGA family) to implement a systolic architecture for a morphology engine. The engine has a 14 bit data-path, a reconfigurable structuring element size and a 512 X 512 image size. We will describe the architecture, the FPGA implementation of the engine and the interface with the host (datacube).

Citation Download Citation

Abdelaziz Chihoub, M. LaValva, J. Avins, and Jeff Turlip "Field-programmable gate array implementation of a systolic architecture for a morphology engine", Proc. SPIE 2064, Machine Vision Applications, Architectures, and Systems Integration II, (6 August 1993); https://doi.org/10.1117/12.150276

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