Paper
2 September 1997 Monitoring process-induced oxide breakdown and its correlation to interface traps
Artur P. Balasinski, R. Hodges, J. Walters, Charles R. Spinner III
Author Affiliations +
Abstract
In-line testing methods of thin gate oxide integrity are compared based on oxide breakdown characteristics. The results were obtained on test structures with plasma induced oxide degradation due to the different plasma based deposition and etch processes used in the five metal CMOS fabrication. Voltage ramp technique has been identified as the most sensitive and universal technique to investigate breakdown characteristics. In order to find out about the possible correlation between the degradation of oxide bulk and the Si/SiO2 interface, trap density in MOSFETs was also monitored using transconductance and charge pumping measurements. It was found that while interface degradation was indeed more severe in the structures showing lower breakdown voltages, no quantitative relationship with breakdown voltage could be established. Process-induced defect distribution across the wafers will also be discussed.
© (1997) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Artur P. Balasinski, R. Hodges, J. Walters, and Charles R. Spinner III "Monitoring process-induced oxide breakdown and its correlation to interface traps", Proc. SPIE 3215, In-Line Characterization Techniques for Performance and Yield Enhancement in Microelectronic Manufacturing, (2 September 1997); https://doi.org/10.1117/12.284673
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KEYWORDS
Oxides

Plasma

Semiconducting wafers

Metals

Field effect transistors

Capacitors

Testing and analysis

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