Standard postprocessing technique for fabrication of large microsuspended structures in CMOS

Bahram Ghodsian; Veljko Milanovic; Orlando Villavicencio

doi:10.1117/12.361212

30 August 1999 Standard postprocessing technique for fabrication of large microsuspended structures in CMOS

Bahram Ghodsian, Veljko Milanovic, Orlando Villavicencio

Proceedings Volume 3874, Micromachining and Microfabrication Process Technology V; (1999) https://doi.org/10.1117/12.361212
Event: Symposium on Micromachining and Microfabrication, 1999, Santa Clara, CA, United States

Abstract

An important problem in silicon micromachining involves fabrication of suspended structures on a chip for both thermal as well as electromagnetic isolations. The problem becomes more pronounced as the size of a suspended structure increase. A new technique to remove the silicon from beneath a large structure, by micromachining for making a suspended microstructure both for thermal, as well as electromagnetic isolations on a CMOS chip is reported. Conventional methods require two steps; front-side etching, isotropic step, followed by an anisotropic etching step. An alternative technique is based on the backside etching process which requires extra masks and processing steps. In order to keep the post-processing steps to a minimum, a simple technique has been developed that exploits the front-side anisotropic etching to a create both under-cuttings as well as deep etching on one single step. This method uses the gate oxide and polysilicon layer in CMOS technology as the sacrificial layer for initiating the under-cutting needed to make a free standing microstructure. The micro-suspension thickness, width and length of 2 micrometers , 150 micrometers X micrometers , respectively, are made out of LPCVD oxide and have been fabricated.

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Bahram Ghodsian, Veljko Milanovic, and Orlando Villavicencio "Standard postprocessing technique for fabrication of large microsuspended structures in CMOS", Proc. SPIE 3874, Micromachining and Microfabrication Process Technology V, (30 August 1999); https://doi.org/10.1117/12.361212

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KEYWORDS

Etching

Anisotropic etching

Oxides

Fabrication

Semiconducting wafers

Silicon

Photomasks

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