Paper
24 March 2006 Imprint technology: A potential low-cost solution for sub-45nm device applications
Author Affiliations +
Abstract
Nano-imprint technology has demonstrated the potential for a low-cost, high-throughput Next Generation Lithography (NGL) method extendable to ultra-fine geometry requirements. Although the development of nano-imprinting lithography has been focused on semiconductor applications, the technology could provide a pathway for non-semiconductor-related applications as well. Examples of technologies that may benefit from this nano-imprint are high-density drives and other stand-alone memories, organic and flexible electronics, photonics, nanoelectronics, biotechnology, etc. With the rapid advances in these industries, the need for sub-nanometer features to drive performance and innovation, while maintaining cost, is to be expected. Step and Flash Imprint Lithography (S-FILTM) is one of several cost-effective imprinting technologies being pursued for sub-100 nm resolution. In demonstrating successful final pattern transfer of features less than 45 nm, S-FIL has sparked some interest as a viable alternative to other NGL methods. Unlike optical-based lithography, imprint utilizes the basic concept of contact printing, and therefore, does not require expensive optics and complex resist material to create images. Thus, the cost of ownership for nano-imprint lithography compared with other optical-based NLGs could provide solutions for many applications. Improvements made in S-FIL in the areas of material dispensing and refinement of the etch barrier (EB) have resulted in more uniform printing while producing a thinner residual layer. These improvements, coupled with changes to the etch processes have enabled pattern transfer with minimal critical dimension (CD) loss. This paper will describe both the new imprinting results and pattern transfer to demonstrate sub-45nm features. CD bias at each of the process steps will also be discussed. Examples of sub-45 nm (1:3) line/space features post imprint and final pattern transfer into oxide will be shown.
© (2006) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Ngoc V. Le, William J. Dauksher, Kathy A. Gehoski, Kevin J. Nordquist, Eric Ainley, and Pawitter Mangat "Imprint technology: A potential low-cost solution for sub-45nm device applications", Proc. SPIE 6151, Emerging Lithographic Technologies X, 61512K (24 March 2006); https://doi.org/10.1117/12.657488
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KEYWORDS
Etching

Lithography

Oxides

Critical dimension metrology

Nanoimprint lithography

Scanning electron microscopy

Semiconducting wafers

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