Full-chip high resolution electron-beam lithography proximity effect correction modeling

Artak Isoyan; Lawrence S. Melvin III

doi:10.1117/12.846681

2 April 2010 Full-chip high resolution electron-beam lithography proximity effect correction modeling

Proceedings Volume 7637, Alternative Lithographic Technologies II; 76370X (2010) https://doi.org/10.1117/12.846681
Event: SPIE Advanced Lithography, 2010, San Jose, California, United States

Abstract

Electron beam lithography (EBL) causes pattern distortions and printability issues during its entire pattern making process, starting from the mask design and finishing with the lithography processes. Hence EBL aerial image formation and proximity correction (PC) modeling becomes more critical and urgent especially for full chip layouts and designs before EBL may be deployed in high-volume manufacturing. This study shows a complete solution for EBL modeling and Electron Beam Proximity Correction (EBPC) correction of full-chip layouts based on aerial image formation through modeling of the e-beam point spread function to assimilate electron beam image formation. The main idea behind the method is to construct a model-based analyses and interpretation of generic pattern distortions of non-corrected representative patterns to achieve the best possible matching of EBL proximity effects with extracted empirical data using an analytical EBL absorbed energy distribution form based on three or more Gaussians, and the form's convolution with representative patterns. Two approaches have been used for EBL model simulation and the comparison of the models is shown. The method has been successfully implemented and integrated into existing tools for modeling.

Citation Download Citation

Artak Isoyan and Lawrence S. Melvin III "Full-chip high resolution electron-beam lithography proximity effect correction modeling", Proc. SPIE 7637, Alternative Lithographic Technologies II, 76370X (2 April 2010); https://doi.org/10.1117/12.846681

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