Paper
3 March 2010 Spacer defined double patterning for sub-72 nm pitch logic technology
Author Affiliations +
Abstract
In order to extend the optical lithography into sub-72 nm pitch regime, spacer defined double patterning as a self-aligning process option was investigated. In the sidewall defined spacer process, spacer material was deposited directly on the resist to achieve process simplification and cost effectiveness. For the spacer defined double patterning, core mandrel CD uniformity is proven to be a main contributor to pitch-walking and defined a new lithographic process window. Here, the aerial image log-slope is shown to be a measurable predictor of CD uniformity and sidewall angle of the resist pattern. Through resist screening and illumination optimization, resist core-mandrel of 2.5 nm CD uniformity across a focus range more than 200 nm with ± 3.5 % exposure latitude was developed having sidewall control close to the normal. Finally etch revealed that pitch-walking post pitch split can be suppressed below 2 nm within ± 2.5 % exposure latitude.
© (2010) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Ryoung-Han Kim, Erin Mclellan, Yunpeng Yin, John Arnold, Sivananda Kanakasabapathy, Sanjay Mehta, Yuansheng Ma, Martin Burkhardt, Jason Cain, Greg McIntyre, Matthew E. Colburn, and Harry J. Levinson "Spacer defined double patterning for sub-72 nm pitch logic technology", Proc. SPIE 7640, Optical Microlithography XXIII, 76400F (3 March 2010); https://doi.org/10.1117/12.846698
Lens.org Logo
CITATIONS
Cited by 3 scholarly publications and 1 patent.
Advertisement
Advertisement
RIGHTS & PERMISSIONS
Get copyright permission  Get copyright permission on Copyright Marketplace
KEYWORDS
Double patterning technology

Critical dimension metrology

Image processing

Photoresist processing

Lithography

Photomasks

Etching

RELATED CONTENT

SAQP and EUV block patterning of BEOL metal layers on...
Proceedings of SPIE (March 24 2017)
Enabling 22-nm logic node with advanced RET solutions
Proceedings of SPIE (March 22 2011)
Double patterning process with freezing technique
Proceedings of SPIE (April 01 2009)
100-nm node lithography with KrF?
Proceedings of SPIE (September 14 2001)

Back to Top