Lithography aware design optimization using ILT

Jaeyoon Jeong; Seokyun Jeong; Changhoon Ahn; Yongsun Jang; Sukjoo Lee; Thomas Cecil; Donghwan Son; Tatung Chow; David Kim

doi:10.1117/12.879393

4 April 2011 Lithography aware design optimization using ILT

Jaeyoon Jeong, Seokyun Jeong, Changhoon Ahn, Yongsun Jang, Sukjoo Lee, Thomas Cecil, Donghwan Son, Tatung Chow, David Kim

Author Affiliations +

Proceedings Volume 7974, Design for Manufacturability through Design-Process Integration V; 797409 (2011) https://doi.org/10.1117/12.879393
Event: SPIE Advanced Lithography, 2011, San Jose, California, United States

Abstract

For increasingly small and dense designs requiring adequate DOF, MEEF, and EL, numerous technologies have been employed to increase yield. Some techniques such as process optimization (i.e. SMO) are effective, but can be costly and time consuming, and are not easily modifiable once an initial choice is made. Design optimization can be done separately from knowledge of the fab's OPC correction, but for sub 32nm nodes the complexity and interaction of the design target shapes is becoming too complicated for predefined design rules to produce an acceptable result. In this paper we introduce a method called Lithographically Enhanced Edge Design (LEED) suited for IDMs. This joint target and mask optimization method takes into account the full OPC correction and process, and modifies the user's design in a controlled way so as to produce a new design with improved lithographic performance which can be used in place of the initial design. Control is given to the user so that inter-layer dependencies are not broken. Also, integrated target, mask, and source optimization is available in cases where target and mask optimization in not sufficient to produce adequate results. The use of ILT allows efficient target, mask, and source correction without extensive user OPC scripting and target modification sweeping. We show LEED results which enable production at 20x node.

Citation Download Citation

Jaeyoon Jeong, Seokyun Jeong, Changhoon Ahn, Yongsun Jang, Sukjoo Lee, Thomas Cecil, Donghwan Son, Tatung Chow, and David Kim "Lithography aware design optimization using ILT", Proc. SPIE 7974, Design for Manufacturability through Design-Process Integration V, 797409 (4 April 2011); https://doi.org/10.1117/12.879393

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available