Charge-Coupled Device Pinning Technologies

James Janesick; Tom Elliott; George Frasehetti; Stewart Collins; Morley Blouke; Brian Corrie

doi:10.1117/12.952516

23 May 1989 Charge-Coupled Device Pinning Technologies

James Janesick, Tom Elliott, George Frasehetti, Stewart Collins, Morley Blouke, Brian Corrie

Proceedings Volume 1071, Optical Sensors and Electronic Photography; (1989) https://doi.org/10.1117/12.952516
Event: OE/LASE '89, 1989, Los Angeles, CA, United States

Abstract

For most thinned silicon CCDs, the photosensitive volume is bounded on top and bottom by layers of silicon dioxide. The frontside oxide is grown to serve as an insulator beneath the conductive gates of the parallel array while the backside oxide forms naturally as the initially bare silicon oxidizes. This paper describes the characteristics of the interface between these oxides and the photo-sensitive silicon and indicates the extent to which CCD performance (e.g. dark current, spectral response, charge collection efficiency, charge transfer efficiency, pixel-nonuniformity read noise full well capacity blooming residual image and vulnerability to ionizing radiation damage) depend* upon these interfacial characteristics. Techniques are described to achieve optimum passivation of these interfaces and to thereby obtain superior performance in the areas just listed. Specifically an implanted structure (the Multi-Pinned-Phase, MPP) is described which provides excellent frontside passivation and several techniques (backside charging, flash gate, the biased flash gate and ion-implantation) are presented for back surface passivation.

Citation Download Citation

James Janesick, Tom Elliott, George Frasehetti, Stewart Collins, Morley Blouke, and Brian Corrie "Charge-Coupled Device Pinning Technologies", Proc. SPIE 1071, Optical Sensors and Electronic Photography, (23 May 1989); https://doi.org/10.1117/12.952516

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