The semiconductor industry has deployed EUV for the latest technology nodes, but the mask making limits have not scaled linearly with the wavelength. Characterization of the tradeoff between ideal placement of subresolution assist features (srafs) versus mask rule constraints (MRC) is needed. In this paper, a simulation study was performed with DUV, low NA EUV, and high NA EUV models on 1D patterns. Using systematic variation, the ideal width and pitch of the primary sraf was identified according to multiple metrics, Image Log Slope (ILS) and process variation (PV) band width. For DUV, optimum sraf placement maintains a large margin between the MRC limits and the sraf printing threshold. However for EUV, the ideal sraf likely violates the MRC minimum width. This is especially true for high NA EUV operating at a low aerial image threshold (AIT), where the ideal sraf width for ILS is only 2 nm. This paper quantifies the degradation in litho quality with the enforcement of increasing MRC limits. Alternative sraf insertion by chopping long srafs into minimum length srafs is applied to prevent sraf printing at MRC valid dimensions, while maintaining improved litho quality over no sraf.
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