Improving the time resolution and sensitivity of Silicon-based Single Photon Avalanche Photodetectors (Si-SPAD) across the entire visible spectrum is critical to improve image quality in biomedical imaging applications such as positron emission tomography or fluorescence lifetime imaging. This work reports on the feasibility of manipulating the penetration depth of photons with 450 nm wavelengths to enhance absorption in Si-SPAD by means of photon trapping structures. Optical-electrical simulations suggest light can be directed towards critical regions of the semiconductor increasing the absorption from 54 to 90% with only 1.2μm of silicon and enhancing the probability of avalanche by electrons that leads to higher multiplication gain and speed of operation.
The implementation of ultra-thin and highly efficient photodetectors and photovoltaic devices is crucial to realize flexible and wearable products in the era of Internet of Things (IoT). CMOS-compatible processing and well-established manufacturing makes Silicon (Si) a great material of choice in many applications but thin crystalline-Si is not as efficient as bulk Si in absorbing light. Light bending phenomenon enabled by micro-/nanoscale holes have been recently demonstrated to achieve high speed Si photodiodes and high efficiency thin crystalline-Si solar cells. Such small-scale devices can be released and transferred from mother substrate to various platforms such as the tips of fiber optic cables for realizing fiber receivers and probing applications in vivo studies. In this study, preliminary results of morphological and electrical characterization of transferred devices are demonstrated and details of the transfer techniques are presented. The quantum efficiency of devices transferred to aluminum coated glass were observed to get enhanced compared to the ones on Si substrate.
Development of cost-effective and power-efficient optical interconnects is required to meet high demand of data transfer in the era of Internet of Things (IoT) that is expected to connect billions of sensors with different functionalities. The cost of optical links must be reduced for a wide adoption of optical interconnects in the fast data transmission systems. Monolithic integration of ultra-fast photodetectors (PDs), one of the major components of optical receivers-with CMOS/BiCMOS circuits, can reduce the cost dramatically. However, expensive material systems and non-CMOS-compatible processing utilized in the current high-speed photodetectors do not promise a monolithic integration to the required circuitry in the near future. On the other hand, high speed PDs with CMOS-compatible material systems such as silicon (Si), germanium (Ge) or SiGe alloys have poor responsivity for the wavelengths of interest at data rates 10 Gb/s or higher. Our solution to this problem is to increase the optical absorption properties of the semiconductor by introducing micro-/nanoscale air holes to the material. Such micro/nanoholes support an ensemble of modes that propagate laterally inside in a very thin layer of semiconductor (<2µm) which is required for high speed operations. The recent demonstration of surface-illuminated high-speed (>25Gb/s) and high efficiency (>50%) Si PDs with integrated micro-/nanoholes proved that light bending can enable ultra-fast Si-based PDs for monolithic integration with CMOS/BiCMOS circuits to realize cost-effective all-Si optical receivers. In this talk, a review of state-of-the art ultra-fast Si PDs for short-reach data communication will be presented and high speed and high efficiency PDs with alternative Si-based material systems will be demonstrated for the applications in long-reach optical links. Future opportunities that light-bending phenomenon can offer in high performance PD design for various applications such as single photon detection, LIDAR and high-performance computing will be discussed.
Micro and nanoscale holes on the surfaces of indirect band gap semiconductors such as silicon can enable perpendicular light bending and trapping of photons to enhance the light material interactions and absorption by orders of magnitude. The ‘bending’ of a vertically oriented light beam at nearly 90 degrees can be visualized as radial waves generated by a pebble dropped into a calm pool of water. Such bending and photon trapping result in an increased optical absorption path enabling very high light absorption coefficients. This observation led to the design of silicon photodetectors with high broadband efficiency above 50% and record ultrafast response contributing to more than 40 billion bits of data per second (Gb/s) communication speed.
Crystalline silicon (c-Si) remains the most commonly used material for photovoltaic (PV) cells in the current commercial solar cells market. However, current technology requires “thick” silicon due to the relative weak absorption of Si in the solar spectrum. We demonstrate several CMOS compatible fabrication techniques including dry etch, wet etch and their combination to create different photon trapping micro/nanostructures on very thin c-silicon surface for light harvesting of PVs. Both, the simulation and experimental results show that these photon trapping structures are responsible for the enhancement of the visible light absorption which leads to improved efficiency of the PVs. Different designs of micro/nanostructures via different fabrication techniques are correlated with the efficiencies of the PVs. Our method can also drastically reduce the thickness of the c-Si PVs, and has great potential to reduce the cost, and lead to highly efficient and flexible PVs.
Photodetectors (PDs) in datacom and computer networks where the link length is up to 300 m, need to handle higher than typical input power used in other communication links. Also, to reduce power consumption due to equalization at high speed (>25Gb/s), the datacom links will use PAM-4 signaling instead of NRZ with stringent receiver linearity requirements. Si PDs with photon-trapping micro/nanostructures are shown to have high linearity in output current verses input optical power. Though there is less silicon material due to the holes, the micro-/nanostructured holes collectively reradiate the light to an in-plane direction of the PD surface and can avoid current crowding in the PD. Consequently, the photocurrent per unit volume remains at a low level contributing to high linearity in the photocurrent. We present the effect of design and lattice patterns of micro/nanostructures on the linearity of ultra-fast silicon PDs designed for high speed multi gigabit data networks.
Nanostructures allow broad spectrum and near-unity optical absorption and contributed to high performance low-cost Si photovoltaic devices. However, the efficiency is only a few percent higher than a conventional Si solar cell with thicker absorption layers. For high speed surface illuminated photodiodes, the thickness of the absorption layer is critical for short transit time and RC time. Recently a CMOS-compatible micro/nanohole silicon (Si) photodiode (PD) with more than 20 Gb/s data rate and with 52 % quantum efficiency (QE) at 850 nm was demonstrated. The achieved QE is over 400% higher than a similar Si PD with the same thickness but without absorption enhancement microstructure holes. The micro/nanoholes increases the QE by photon trapping, slow wave effects and generate a collective assemble of modes that radiate laterally, resulting in absorption enhancement and therefore increase in QE. Such Si PDs can be further designed to enhance the bandwidth (BW) of the PDs by reducing the device capacitance with etched holes in the pin junction. Here we present the BW and QE of Si PDs achievable with micro/nanoholes based on a combination of empirical evidence and device modeling. Higher than 50 Gb/s data rate with greater than 40% QE at 850 nm is conceivable in transceivers designed with such Si PDs that are integrated with photon trapping micro and nanostructures. By monolithic integration with CMOS/BiCMOS integrated circuits such as transimpedance amplifiers, equalizers, limiting amplifiers and other application specific integrated circuits (ASIC), the data rate can be increased to more than 50 Gb/s.
We present a CMOS compatible fabrication technique to create micro/nanostructures on silicon and germanium surfaces for effective photon trapping and enhanced absorption. We achieved many times of absorption enhancement enabled by these photon trapping micro/nanostructures compared to bulk silicon and germanium counterparts. This method can lead to designing both highly efficient photovoltaics, ultra-fast photodetectors and highly sensitive photon counting devices with dramatically reduced device thickness. We also demonstrate that different fabrication techniques (dry etch, wet etch, and their combination) and different geometries of these micro/nanostructures can affect the ability and extent of the photon trapping and light manipulation in semiconductor.
High-aspect ratio semiconductor pillar- and hole-based structures are being investigated for photovoltaics, energy harvesting devices, transistors, and sensors. The fabrication of pillars and holes frequently involves top-down fabrication (such as dry etching) of semiconductors. Such a process contributes to different types of crystalline defects including vacancies, interstitials, dislocations, stacking faults, surface roughness, impurities, and charging effects. These defects contribute to degraded device characteristics impacting detection sensitivity, energy conversion efficiency, etc. In this presentation, we review dry-etched semiconductor devices and demonstrate several possible methods to inhibit device degradation induced by surface damage. These methods include hydrogen passivation, the growth of oxide passivating thin films using wet furnace growth, and low-ion energy etching. These methods contributed to a leakage current reduction by as much as four orders of magnitude.
We report the use of sol-gel method at room ambient to grow nanoscale thin film of Ga2O3 on Si surface for both surface
passivation and gate dielectric. The admittance measurements were carried out in the frequency range of 20 kHz-1 MHz
at room temperature. Voltage dependent profile of interfacial trap density (Dit) was obtained by using low and high
frequency capacitance method. The capacitance (C)-voltage (V) analyses show that the structures have a low interfacial
trap density (Dit) of 1x1012 cm-2eV-1. The Ga2O3 thin film synthesized via sol-gel method directly on devices to function
as a gate dielectric film is found to be very effective. We also present our experimental results for a number of gate
dielectric and device passivation applications.
Efficient light harvesting in a thin layer of crystalline Si can be realized by implementing nanoscale pillars and holes to the device structure. The major drawback of the pillars and holes based photovoltaic devices is high surface to volume ratio, contributing to an increase in surface recombination rate of the photo-generated carriers. The common techniques used in pillars/holes fabrication such as dry etching make the surface even worse by bombarding it with high energy ions. Therefore, such damaged surfaces of high aspect ratio structures need to be effectively passivated. In this study, we demonstrate a hole based thin crystalline Si photovoltaic device with enhanced open circuit voltage and short circuit current after a successful surface passivation process through a wet oxidation. In addition, the effect of passivation layer fabricated by rapid thermal oxide growth on photo response is investigated. A successful fabrication of thin crystalline Si solar cells can lead to the applications of ultra-thin, highly efficient, flexible and wearable energy sources.
In this work, pure and IIIA element doped ZnO thin films were grown on p type silicon (Si) with (100) orientated surface by sol-gel method, and were characterized for comparing their electrical characteristics. The heterojunction parameters were obtained from the current-voltage (I-V) and capacitance-voltage (C-V) characteristics at room temperature. The ideality factor (n), saturation current (Io) and junction resistance of ZnO/p-Si heterojunction for both pure and doped (with Al or In) cases were determined by using different methods at room ambient. Other electrical parameters such as Fermi energy level (EF), barrier height (ΦB), acceptor concentration (Na), built-in potential (Φi) and voltage dependence of surface states (Nss) profile were obtained from the C-V measurements. The results reveal that doping ZnO with IIIA (Al or In) elements to fabricate n-ZnO/p-Si heterojunction can result in high performance diode characteristics.
The glancing angle deposition (GLAD) technique, unlike a conventional physical vapor deposition (PVD) process,
incorporates a flux of atoms that are obliquely incident on a tilted and rotating substrate. Instead of a continuous thin
film coating, these atoms can form arrays of three-dimensional nanostructures due to a shadowing effect. By simply
controlling the deposition angle and substrate rotation speed, nanostructures of a large variety of materials in the shapes
of rods, screws, or springs can be obtained easily that are otherwise difficult to produce by conventional lithographical
techniques. In this study, a brief overview of the growth mechanisms of GLAD nanostructures is presented. In addition,
a new small angle deposition (SAD) technique as a simple means of conformally coating nanorod or nanowire arrays is
described. SAD utilizes a small tilt angle during PVD on nanostructured substrates, which allows the effective exposure
of nanorod sidewalls to the incoming flux and leads to enhanced thin film conformality. In this work, some recent results
on core-shell nanorod arrays obtained by coating GLAD nanorods with a SAD shell will be presented. It will be shown
that core-shell nanostructured geometries obtained by the simple SAD-GLAD method can significantly enhance catalyst
activity for fuel cell electrodes, and charge carrier collection efficiency in photoconductive/semiconductor
nanostructured materials.
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