Chemical mechanical polishing (CMP) is a technique which helps to print a smaller depth of
focus and smoother surface in micro fabrication industry. In this project, boron doped polysilicon
is used as a fill material for Through Silicon Vias (TSV) creating a 3D package. It is shown that
the presence of boron as dopant suppresses the polysilicon polish rate. To increase the polish
rate, understanding the mechanism of polish rate retardation is essential. We believe that the
electrical effects play the major role in this phenomenon and by reducing this effect we are able
to increase the polish rate.
As integrated circuit interconnect dimensions continue to shrink and signaling frequencies increase, interconnect performance degrades. The performance degradation is due to several factors such as power consumption, cross-talk, and signal attenuation. On-chip optical interconnects are a potential solution to these scaling issues because they offer the promise of providing higher bandwidth. In this paper, progress on the major on-chip optical building blocks will be reviewed. It will be shown that significant advances have been made in the design and fabrication of waveguides, detectors, and couplers. However, major challenges in high speed electrical to optical conversion and signaling remain.
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